• 한국전기전자재료학회논문지
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• 제11권2호
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• pp.106-110
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• 1998

The $LiNbO_3$ thin films were prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. RTA(Rapid Thermal Annealing) treatment was performed for as-deposited films in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric $LiNbO_3$ film was increased from a typical value of $1{\sim}2{\times}10^8{\Omega}{\cdot}cm$ before the annealing to about $1{\times}10^{13}{\Omega}{\cdot}cm$ at 500 kV/cm and reduced the interface state density of the $LiNbO_3/Si$ (100) interface to about $1{\times}10^{11}/cm^2{\cdot}eV$. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization ($P_r$) and coercive field ($E_c$) values of about 1.2 ${\mu}C/cm^2$ and 120 kV/cm, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.93-93
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• 2007

We present a mechanism for stress-induced interface degrdadations through ab initio pseudopotential calculations. We find that N interstitials at the interface create various defects levels in the Si band gap, which range from the mid gap to the conduction band of Si. The level positions are dependent on the configuration of oxygen toms around the N interstitial. On the other hand, the mid-gap level caused by Pb center is possibly removed by substitution of a N atom for a threefold-coordinated Si atom in the defect. Our calculations explain why interface state generations are enhanced in Si oxynitride, especially near conduction band edge of Si, although densities of Pb center are reduced.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.66-69
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• 2018

This study was researched the electrical properties of semiconductor devices such as ITO, $SiO_2$, $V_2O_5$ thin films. The films of ITO, $SiO_2$, $V_2O_5$ were deposited by the rf magnetron sputtering system with mixed gases of oxygen and argon to generate the plasma. All samples were cleaned before deposition and prepared the metal electrodes to research the current-voltage properties. The electrical characteristics of semiconductors depends on the interface's properties at the junction. There are two kinds of junctions such as ohmic and schottky contacts in the semiconductors. In this study, the ITO thin film was shown the ohmic contact properties as the linear current-voltage curves, and the electrical characteristics of $SiO_2$ and $V_2O_5$ films were shown the non-linear current-voltage curves as the schottky contacts. It was confirmed that the electronic system with schottky contacts enhanced the electronic flow owing to the increment of efficiency and increased the conductivity. The schottky contact was only defined special characteristics at the semiconductor and the interface depletion layer at the junction made the schottky contact which has the effect of leakage current cutoff. Consequently the semiconductor device with shottky contact increased the electronic current flow, in spite of depletion of carriers.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.193.2-193.2
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• 2016

We evaluate the change in defects in the oxidized SiO2 grown on 4H-SiC (0001) by plasma assisted oxidation, by comparing with that of conventional thermal oxide. In order to investigate the changes in the electronic structure and electrical characteristics of the interfacial reaction between the thin SiO2 and SiC, x-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), DFT calculation and electrical measurements were carried out. We observed that the direct plasma oxide grown at the room temperature and rapid processing time (300 s) has enhanced electrical characteristics (frequency dispersion, hysteresis and interface trap density) than conventional thermal oxide and suppressed interfacial defect state. The decrease in defect state in conduction band edge and stress-induced leakage current (SILC) clearly indicate that plasma oxidation process improves SiO2 quality due to the reduced transition layer and energetically most stable interfacial state between SiO2/SiC controlled by the interstitial C.

• E2M - 전기 전자와 첨단 소재
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• 제10권7호
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• pp.659-667
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• 1997

The influence of SiO$_2$on the microstructure and electrical properties of zinc oxide varistor was investigated. Zn$_2$SiO$_4$third phase in the sintered body was found at grain boundaries, multiple grain junctions, and occasionally within ZnO grains. This phase acted as a grain growth inhibitor, which retard the grain growth of the ZnO matrix by impeding migration on the grain boundaries. As SiO$_2$ addition increases, average grain size decreased from 40.6${\mu}{\textrm}{m}$ to 26.9${\mu}{\textrm}{m}$ due to the pinning effect by Zn$_2$SiO$_4$ and drag effect by Si segregation at grain boundaries, the breakdown voltage consequently increased. When SiO$_2$ addition is increased, interface state density decreased, however, the barrier height increased by decrease of donor concentration, as a result, the nonlinear exponent increased and leakage current decreased. While, as SiO$_2$ addition increase, it was found that the apparent dielectric loss factor shows a tendency of decrease. Wholly, electrical properties of zinc oxide varistor can be said to be improved by SiO$_2$addition.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 춘계종합학술대회
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• pp.501-504
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• 2003

본 연구에서는 박막트랜지스터의 특성 향상을 위하여 강유전성 박막을 게이트 절연충으로 사용하기 위하여 강유전성 박막과 a-Si:H 의 계면특성을 조사하였다. 먼저 강유전성 박막 중에 대표적인 SrTiO$_3$를 E-BEAM 증착기로 박막을 형성시켰다. 형성된 박막은 $N_2$ 분위기에서 15$0^{\circ}C$~$600^{\circ}C$로 1시간 ANNEALING 하여 전자현미경으로 표면을 측정하였다. SrTiO$_3$의 유전상수는 50~100 정도였으며 항복전계는 1~l.5 MV/cm로 매우 우수한 유전특성을 갖고 있었다. 강유전체 박막 위에 a-SiN:H,a-Si:H(n-type a-Si:H) 등을 PECVD로 증착하여 MFNS구조를 형성하였다. 계면특성을 C-V PLOTTER로 측정한 결과 SrTiO$_3$ 박막은 SiN 과의 접합이 매우 안정되어 있었고 C-V특성은 SiN/a-Si:H 과 유사하였다. 그러나 FERROELECTRIC/a-S:H의 경우가 훨씬 CAPACITANCE값이 컸으며, 이는 강유전체 박막의 높은 유전상수에 기인 된 것이라 생각된다.

• 한국결정성장학회지
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• 제11권1호
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• pp.38-42
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• 2001

Electric and dielectric(Ba,Sr)$TiO_3$[BST] thin films for emtal-Insulator-Semiconductor(MIS) capacitors have been studied. BST thin films wre deposted on p-Si(100) substrates bythe RF magnetron sputtering with tempratue range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of Al/BST/$SiO_2$/Si sandwich structure were evaluated ot redcue the leakage current density. The charge state densities of the MIS capacitors were determined by high frequency (1 MHz) C-V measurement. In order to reduce the leakage current in MIS capacitor, high quality $SiO_2$ layer was deposited on bare p-Si substrate. Depending on the oxygen pressure and substrate temperature both positive and negative polarities of effective oxide charge in the MIS capacitors were evaluated. It is considered that the density of electronic states, generated at the BST/$SiO_2$/p-Si interface due to the asymmetric structure within BST/$SiO_2$/Si structure, and the oxygen vacancy content has influence on the behavior of oxide charge.

• 전자공학회논문지A
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• 제33A권3호
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• pp.117-125
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• 1996

The variation of the interfacial and the electrical properties of SiO$_{2}$TiW layers as a function of anneal temperature was extensively investigated. During the deposition of SiO$_{2}$ on TiW chemical bonds such as SiO$_{2}$, TiW, WO$_{3}$, WO$_{2}$ TiO$_{2}$ Ti$_{2}$O$_{5}$ has been created at the SiO$_{2}$/TiW interface. At the anneal temperature of 300$^{\circ}C$, WO$_{3}$ and TiO$_{2}$ bonds started to break due to the reduction phenomena of W and Ti and simultaneously the metallic W and Ti bonds started to create. Above 500$^{\circ}C$, a part of Si-O bonds was broken and consequently Ti/W silicide was formed. Form the current-voltage characteristics of Al/Sico$_{2}$(220$\AA$)/TiW antifuse structure, it was found that the breakdown voltage of antifuse device wzas decreased with increasing annealing temperature for SiO$_{2}$(220$\AA$)/TiW layer. When r, the insulating property of antifuse device of the deterioration of intermetallic SiO$_{2}$ film, caused by the influw of Ti and W.W.

• 한국재료학회지
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• 제21권6호
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• pp.341-346
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• 2011

In this study, we inserted a Zn buffer layer into a AZO/p-type a-si:H layer interface in order to lower the contact resistance of the interface. For the Zn layer, the deposition was conducted at 5 nm, 7 nm and 10 nm using the rf-magnetron sputtering method. The results were compared to that of the AZO film to discuss the possibility of the Zn layer being used as a transparent conductive oxide thin film for application in the silicon heterojunction solar cell. We used the rf-magnetron sputtering method to fabricate Al 2 wt.% of Al-doped ZnO (AZO) film as a transparent conductive oxide (TCO). We analyzed the electro-optical properties of the ZnO as well as the interface properties of the AZO/p-type a-Si:H layer. After inserting a buffer layer into the AZO/p-type a-Si:H layers to enhance the interface properties, we measured the contact resistance of the layers using a CTLM (circular transmission line model) pattern, the depth profile of the layers using AES (auger electron spectroscopy), and the changes in the properties of the AZO thin film through heat treatment. We investigated the effects of the interface properties of the AZO/p-type a-Si:H layer on the characteristics of silicon heterojunction solar cells and the way to improve the interface properties. When depositing AZO thin film on a-Si layer, oxygen atoms are diffused from the AZO thin film towards the a-Si layer. Thus, the characteristics of the solar cells deteriorate due to the created oxide film. While a diffusion of Zn occurs toward the a-Si in the case of AZO used as TCO, the diffusion of In occurs toward a-Si in the case of ITO used as TCO.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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• pp.116-119
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• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.