• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.644-647
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• 2001

The investigations were discussed on the radiation effects of the electrical properties to the p-type MOS capacitors, which were irradiated by cobalt-60 gamma ray sources. The characteristics of capacitance-bias voltage(C-V) and of dielectric dissipation tarter-bias voltage(D-V) on the capacitors were measured at 1 [MHz] frequency. The microscopic behaviors of spate charges in oxide and silicon-silicon dioxide(Si- $SiO_2$) interface were investigated from the experimental data. The C-V characteristics are statical and convenient for the evaluation of the steady state behavior of carriers and interface states characteristics. While, the distribution and magnitude of space charges in oxide can be found out accurately on the $V_{dp}$ in D-V curves. The density of interface states can be deduced with ease from the magnitude of D-peak at depletion state. Thus, it is also concluded that the D-V curves are more useful and easier than conventional C-V curves for analysis of the microscopic and dynamic behavior of carriers in oxide and Si- $SiO_2$interface.

• Journal of the Korean Ceramic Society
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• v.42 no.9 s.280
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• pp.624-630
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• 2005

To investigate the possibility of the $ZrO_2$ buffer layer as the insulator for the Metal-Ferroelectric-Insulator-semiconductor (MFIS) structure, $ZrO_2$ and $SrBi_2Ta_2O_9$ (SBT) thin films were deposited on the P-type Si(111) wafer by the R.F. magnetron-sputtering method. According to the process with and without the post-annealing of the $ZrO_2$ buffer layer and SBT thin film, the diffusion amount of Sr, Bi, Ta elements show slight difference through the Glow Discharge Spectrometer (GDS) analysis. From X-ray Photoelectron Spectroscopy (XPS) results, we could confirm that the post-annealing process affects the chemical binding condition of the interface between the $ZrO_2$ thin film and the Si substrate. Compared to the MFIS structure without the post-annealing of the $ZrO_2$ buffer layer, memory window value of MFlS structure with post-annealing of the $ZrO_2$ buffer layer were considerably improved. The window memory of the Pt/SBT (260 nm, $800^{\circ}C)/ZrO_2$ (20 nm) structure increases from 0.75 to 2.2 V under the applied voltage of 9 V after post-annealing.

• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.389-396
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• 2008

The effect of thermal cycling on bond strength and residual stress at the interface between benzocyclobutene (BCB) and plasma enhanced chemical vapor deposited (PECVD) silicon dioxide ($SiO_2$) coated silicon wafers were evaluated by four point bending and wafer curvature techniques. Wafers were bonded using a pre-established baseline process. Thermal cycling was done between room temperature and a maximum peak temperature. In thermal cycling performed with 350 and $400^{\circ}C$ peak temperature, the bond strength increased substantially during the first thermal cycle. The increase in bond strength is attributed to the relaxation in residual stress by the condensation reaction of the PECVD $SiO_2$: this relaxation leads to increases in deformation energy due to residual stress and bond strength.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.193-193
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• 2012

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is the most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. Single-chamber PECVD system for a-Si:H solar cell manufacturing has the advantage of lower initial investment and maintenance cost for the equipment. However, in single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of single-chamber PECVD system. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. In order to remove the deposited B inside of the plasma chamber during p-layer deposition, a high RF power was applied right after p-layer deposition with SiH4 gas off, which is then followed by i-layer, n-layer, and Ag top-electrode deposition without vacuum break. In addition to the p-i interface control, various interface control techniques such as FTO-glass pre-annealing in O2 environment to further reduce sheet resistance of FTO-glass, thin layer of TiO2 deposition to prevent H2 plasma reduction of FTO layer, and hydrogen plasma treatment prior to n-layer deposition, etc. were developed. The best initial solar cell efficiency using single-chamber PECVD system of 10.5% for test cell area of 0.2 $cm^2$ could be achieved by adopting various interface control methods.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.3
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• pp.127-131
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• 2001

The effect of grain shape on the grain growth behavior of oxide system was investigated as afunction of liquid content during liquid phase sintering. As a model system, the solid grains of $Al_{2}O_{3}$ and MgO were selected during liquid phase sintering, i.e. faceted shape of $Al_{2}O_{3}$ in $CaAl_{2}Si_{2}O_{8}$ liquid phase and spherical shape of MgO in $CaMgSiO_{4}$ liquid phase. The average grain size of MgO with spherical shape was decreased with increasing the liquid phase content, whereas that of $Al_{2}O_{3}$ with faceted shape was independent of liquid phase content. In the case of $Al_{2}O_{3}$ grains with faceted shape, which interfaces are expected to be atomically flat, are likely to grow by the interfacial reaction controled process. Whereas, in the case of MgO grains with spherical shape, which interface are expected to be atomically rough, are likely to grow by the diffusion controlled process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.58.1-58.1
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• 2010

We have developed a novel crystallization process, where the crystallization temperature is lowered compared to the conventional RTA process and the metal contamination is lowered compared to the conventional VIC process. A very-thin a-Si film was deposited and crystallized at $550^{\circ}C$ for 3 h by the VIC process and then a thick a-Si film was deposited and crystallized by the RTA process at $680^{\circ}C$ for 5 min using the VIC poly-Si layer as a crystallization seed layer. The RTA crystallized temperature could be lowered up to $50^{\circ}C$, compared to RTA process alone. The poly-Si film appeared a needle-like growth front and relatively well-arranged (111) orientation. In addition, the Ni concentration in the poly-Si film was lowered to $3{\times}10^{17}\;cm^{-3}$ and that at the poly-Si/$SiO_2$ interface was lowered to $5{\times}10^{19}\;cm^{-3}$. The reduction in metal contamination could be greatly helpful to achieve a low leakage current in poly-Si TFT, which is the critical parameter for commercialization of AMOLED.

• Applied Microscopy
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• v.29 no.3
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• pp.281-289
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• 1999

The stirred and thixoformed $SiC_p/AZ91HP$ Mg composites are studied on the basis of microstructural analysis using transmission electron microscopy (TEM). The products of interfacial reaction are identified as $Mg_2Si$, MgO and $Mg_{17}Al_{12}$ phases and the crystallized phases are found to be orthorhmbic $Al_6Mn$ and decagonal T phases. It is shown that $Mg_2Si$ and $Mg_{17}Al_{12}$ phases are found at the surface of $SiC_p$ and $Al_6Mn$ is found near interface and crystallized on the matrix. Phase identification is carried out by crystallographic work based on primitive cell volume, zero order Laue zone (ZOLZ) patterns and single convergent beam electron diffraction (CBED) patterns containing higher order Laue zone ring from a nanosized region.

• Journal of the Korean Magnetics Society
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• v.16 no.6
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• pp.279-282
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• 2006

Magnetic tunnel junctions (MTJs), which consisted of amorphous ferromagnetic NiFeSiB free layers, were investigated. The NiFeSiB layers were used to substitute for the traditionally used CoFe and/or NiFe layers with the emphasis being given to obtaining an understanding of the effect of the amorphous free layer on the switching characteristics of the MTJs. $Ni_{16}Fe_{62}Si_{8}B_{14}$ has a lower saturation magnetization ($M_{s}:\;800\;emu/cm^{3}$) than $Co_{90}Fe_{10}$ and a higher anisotropy constant ($K_{u}:\;2700\;erg/cm^{3}$) than $Ni_{80}Fe_{20}$. The $Si/SiO_{2}/Ta$ 45/Ru 9.5/IrMn 10/CoFe $7/AlO_{x}/CoFeSiB\;(t)/Ru\;60\;(in\;nanometers)$structure was found to be beneficial for the switching characteristics of the MTJ, leading to a reduction in the coercivity ($H_{c}$) and an increase in the sensitivity resulted from its lower saturation magnetization and higher uniaxial anisotropy. Furthermore, by inserting a very thin CoFe layer at the tunnel barrier/NiFeSiB interface, the TMR ratio and switching squareness were improved more with the increase of NiFeSiB layer thickness up to 11 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2899-2904
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• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.