• Title/Summary/Keyword: $SiO_2/Si$ interface

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Microstructural analysis and characterization of 1-D ZnO nanorods grown on various substrates (다양한 기판위에 성장한 1차원 ZnO 나노막대의 특성평가 및 미세구조 분석)

  • Kong, Bo-Hyun;Kim, Dong-Chan;Cho, Hyung-Koun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.116-117
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    • 2006
  • I-D ZnO nanostructures were fabricated by thermal evaporation method on Si(100), GaN and $Al_2O_3$ substrates without a catalyst at the reaction temperature of $700^{\circ}C$. Only pure Zn powder was used as a source material and Ar was used as a carrier gas. The shape and growth direction of synthesized ZnO nanostructures is determined by the crystal structure and the lattice mismatch between ZnO and substrates. The ZnO nanostructure on Si substrate were inclined regardless of their substrate orientation. The origin of ZnO/Si interface is highly lattice-mismatched and the surface of the Si substrate inevitably has the $SiO_2$ layer. The ZnO nanostructure on the $Al_2O_3$ substrate was synthesized into the rod shape and grown into particular direction. For the GaN substrate, however, ZnO nanostructure with the honeycomb-like shape was vertically grown, owing to the similar lattice parameter with GaN substrate.

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The Effects of Composition on the Interface Resistance in Bi-System Glass Frit (Bi 계열 Glass Frit 조성이 계면저항에 미치는 영향)

  • Kim, In Ae;Shin, Hyo Soon;Yeo, Dong Hun;Jeong, Dae Yong
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.12
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    • pp.858-862
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    • 2013
  • The front electrode should be used to make solar cell panel so as to collect electron. The front electrode is used by paste type, printed on the Si-solar cell wafer and sintered at about $800^{\circ}C$. The paste is composed Ag powder and glass frit which make the ohmic contact between Ag electrode and n-type semiconductor layer. From the previous study, the Ag electrodes which used two commercial glass frit of Bi-system were so different on the interface resistance. The main composition of them was Bi-Zn-B-Si-O and few additives added in one of them. In this study, glass frit was made with the ratio of $Bi_2O_3$ and ZnO on the main composition, and then paste using glass frit was prepared respectively. And, also, the paste using the glass frit added oxide additives were prepared. The change of interface resistance was not large with the ratio of $Bi_2O_3$ and ZnO. In the case of G6 glass frit, 78 wt% $Bi_2O_3$ addition, the interface resistance was $190{\Omega}$ and most low. In the glass frit added oxide, the case of Ca increased over 10 times than it of G6 glass frit on the interface resistance. It was thaught that after sintering, Ca added glass frit was not flowed to the interface between Ag electrode and wafer but was in the Ag electrode.

The Effects of Sliding Speed and Load on Tribological Behavior of Ceramics in Line-contact Sliding (선접촉시 세라믹의 마찰 및 마멸 특성에 미치는 속도와 하중의 영향)

  • 김영호;이영제
    • Tribology and Lubricants
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    • v.11 no.4
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    • pp.35-44
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    • 1995
  • Within the practical ranges of speed and load, the formation of transfer films and the consequent effects on the friction and wear behavior of ceramic materials during repeated pass sliding contact were studied. These tests were done using $Al_{2}O_{3}$, SiC and $Si_{3}N_{4}$ with the cylinder-on-flat test configuration. The three pairings behaved differently, even if some wear mechanisms were common to the three systems. The $Al_{2}O_{3}$ pair showed the least wear in overall conditions, followed by the $Si_{3}N_{4}$ pair in harder sliding conditions. The wear of SiC was very high at severe loading. In case of $AL_{2}O_{3}$ and $Si_{3}N_{4}$, the transfer film, whenever formed, is strongly attached, enough to resist being wiped off by the slider. As a consequence, the formation of this f'fim leads to a decrease in the wear rate because of the protecting role of the film. The presence of the film at the contact interface also results in high friction. Also, the wear rate of each ceramics is related to the frictional power provided by load, speed and friction.

Atomic Layer Deposition of HfO2 Films on Ge

  • Cho, Young Joon;Chang, Hyo Sik
    • Applied Science and Convergence Technology
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    • v.23 no.1
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    • pp.40-43
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    • 2014
  • We investigated the growth characteristics and interfacial properties of $HfO_2$ films deposited on Ge substrate through atomic layer deposited (ALD) by using an in-situ medium energy ion scattering analysis. The growth kinetics of $HfO_2$ grown on a $GeO_2/Ge$ substrate through ALD is similar to that grown on an $SiO_2/Si$ substrate. However, the incubation period of $HfO_2$ deposition on Ge is shorter than that on Si. The $HfO_2$ grown on the GeO/Ge substrate shows a significant diffusion of Hf atoms into the substrate interface and GeO volatilization after annealing at $700^{\circ}C$. The presence of low-quality Ge oxide or suboxide may degrade the electrical performance of device.

Progess in Fabrication Technologies of Polycrystalline Silicon Thin Film Transistors at Low Temperatures

  • Sameshima, T.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.129-134
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    • 2004
  • The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

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Characterization of ultrathin ONO stacked dielectric layers for NVSM (NVSM용 초박막 ONO 적층 유전층의 특성)

  • 이상은;김선주;서광열
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.8 no.3
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    • pp.424-430
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    • 1998
  • Film characteristics of thin ONO dielectric layers for MONOS (metal-oxide-nitride-oxide-semiconductor) EEPROM was investigated by AES, SIMS, TEM and AFM. The ONO films with different dimension of tunneling oxide, nitride, and blocking oxide were fabricated. During deposition of the LPCVD nitride films on tunneling oxide, this thin oxide was nitrized. When the blocking oxide were deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of $SiO_2$(blocking oxide)/O-rich SiOxNy (interface)/ N-rich SiOxNy(nitride)/O-rich SiOxNy(tunneling oxide). In addition, the SiON phase is distributed mainly near the tunneling oxide/nitride and nitride/blocking oxide interfaces, and the $Si_2NO$ phase is distributed mainly at nitride side of each interfaces and in tunneling oxide.

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Removal of Metallic Impurity at Interface of Silicon Wafer and Fluorine Etchant (실리콘기판과 불소부식에 표면에서 금속불순물의 제거)

  • Kwack, Kwang-Soo;Yoen, Young-Heum;Choi, Seung-Ok;Jeong, Noh-Hee;Nam, Ki-Dae
    • Journal of the Korean Applied Science and Technology
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    • v.16 no.1
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    • pp.33-40
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    • 1999
  • We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.

The $Al_2O_3$ Passivation Mechanism for c-Si Surface Deposited by ALD Using $O_3$ Oxidant

  • Jo, Yeong-Jun;Jang, Hyo-Sik
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.320.1-320.1
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    • 2013
  • We have investigated the effect of surface passivation for crystalline silicon solar cell using ozone-based atomic layer deposited (ALD) $Al_2O_3$. We examined passivation properties such as uniformity, carrier lifetime, thickness, negative fixed charge density at AlOx/Si interface, and reflectance. The influences of process temperature and heat treatment were investigated using microwave photoconductance decay (PCD). Ozone-based ALD $Al_2O_3$ film shows the best carrier lifetime at lower deposition temperature than $H_2O$-based ALD.

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A Study on the Memory Trap Analysis and Programming Characteristics of Reoxidized Nitrided Oxide (재산화 질화산화막의 기억트랩 분석과 프로그래밍 특성)

  • Nam, Dong-Woo;An, Ho-Myung;Han, Tae-Hyun;Seo, Kwang-Yell;Lee, Sang-Eun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.17-20
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    • 2001
  • Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35{\mu}m$ Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by $0.35{\mu}m$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and $Si_{2}NO$ species near the new $Si-SiO_{2}$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the $Si-SiO_{2}$ interface and contributed to electron trap generation.

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Electrical Characteristics of SiC MOSFET Utilizing Gate Oxide Formed by Si Deposition (Si 증착 이후 형성된 게이트 산화막을 이용한 SiC MOSFET의 전기적 특성)

  • Young-Hun Cho;Ye-Hwan Kang;Chang-Jun Park;Ji-Hyun Kim;Geon-Hee Lee;Sang-Mo Koo
    • Journal of IKEEE
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    • v.28 no.1
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    • pp.46-52
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    • 2024
  • In this study, we investigated the electrical characteristics of SiC MOSFETs by depositing Si and oxidizing it to form the gate oxide layer. A thin Si layer was deposited approximately 20 nm thick on top of the SiC epi layer, followed by oxidation to form a gate oxide layer of around 55 nm. We compared devices with gate oxide layers produced by oxidizing SiC in terms of interface trap density, on-resistance, and field-effect mobility. The fabricated devices achieved improved interface trap density (~8.18 × 1011 eV-1cm-2), field-effect mobility (27.7 cm2/V·s), and on-resistance (12.9 mΩ·cm2).