• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.75.2-75.2
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• 2010

We studied the fabrication of polycrystalline silicon (pc-Si) films as seed layers for application of pc-Si thin film solar cells, in which amorphous silicon (a-Si) films in a structure of glass/Al/$Al_2O_3$/a-Si are crystallized by the aluminum-induced layer exchange (ALILE) process. The properties of pc-Si films formed by the ALILE process are strongly determined by the oxide layer as well as the various process parameters like annealing temperature, time, etc. In this study, the effects of the oxide film thickness on the crystallization of a-Si in the ALILE process, where the thickness of $Al_2O_3$ layer was varied from 4 to 50 nm. For preparation of the experimental film structure, aluminum (~300 nm thickness) and a-Si (~300 nm thickness) layers were deposited using DC sputtering and PECVD method, respectively, and $Al_2O_3$ layer with the various thicknesses by RF sputtering. The crystallization of a-Si was then carried out by the thermal annealing process using a furnace with the in-situ microscope. The characteristics of the produced pc-Si films were analyzed by optical microscope (OM), scanning electron microscope (SEM), Raman spectrometer, and X-ray diffractometer (XRD). As results, the crystallinity was exponentially decayed with the increase of $Al_2O_3$ thickness and the grain size showed the similar tendency. The maximum pc-Si grain size fabricated by ALILE process was about $45{\mu}m$ at the $Al_2O_3$ layer thickness of 4 nm. The preferential crystal orientation was <111> and more dominant with the thinner $Al_2O_3$ layer. In summary, we obtained a pc-Si film not only with ${\sim}45{\mu}m$ grain size but also with the crystallinity of about 75% at 4 nm $Al_2O_3$ layer thickness by ALILE process with the structure of a glass/Al/$Al_2O_3$/a-Si.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.53-54
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• 2013

Nano-multilayered CrAlSiN films consisting of crystalline CrN nanolayers and amorphous AlSiN nanolayers were deposited by cathodic arc plasma deposition. Their oxidation characteristics were studied between 600 and $1000^{\circ}C$ for up to 70 h in air. During their oxidation, the amorphous AlSiN nanolayers crystallized. The formed oxides consisted primarily of $Cr_2O_3$, ${\alpha}-Al_2O_3$, $SiO_2$. The outer $Al_2O_3$ layer formed by outward diffusion of Al ions. Simultaneously, an inner ($Al_2O_3$, $Cr_2O_3$)-mixed layer formed by the inward diffusion of oxygen ions. $SiO_2$ was present mainly in the lower part of the oxide layer due to its immobility. The CrAlSiN films displayed good oxidation resistance, owing to the formation of oxide crystallites of $Cr_2O_3$, ${\alpha}-Al_2O_3$, and amorphous $SiO_2$.

• Journal of the Korean Ceramic Society
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• v.42 no.2 s.273
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• pp.104-109
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• 2005

To study the role of PbO as the buffer layer, Pt/PZT/PbO/Si with the MFIS structure was deposited on the p-type (100) Si substrate by the r.f. magnetron sputtering with $Pb_{1.1}Zr_{0.53}Ti_{0.47}O_3$ and PbO targets. When PbO buffer layer was inserted between the PZT thin film and the Si substrate, the crystallization of the PZT thin films was considerably improved and the processing temperature was lowered. From the result of an X-ray Photoelectron Spectroscopy (XPS) depth profile result, we could confirm that the substrate temperature for the layer of PbO affects the chemical states of the interface between the PbO buffer layer and the Si substrate, which results in the inter-diffusion of Pb. The MFIS with the PbO buffer layer show the improved electric properties including the high memory window and low leakage current density. In particular, the maximum value of the memory window is 2.0V under the applied voltage of 9V for the Pt/PZT(200 nm, $400^{\circ}C)/PbO(80 nm)/Si$ structures with the PbO buffer layer deposited at the substrate temperature of $300^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.240.2-240.2
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• 2013

The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

• Journal of the Korean Ceramic Society
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• v.28 no.8
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• pp.625-625
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• 1991

The specimens for the corrosion test were made by hot-pressing of SiC power with 2 wt% Nl2O3 and 10wt% Al2O3 additions at 2000℃ and 2050℃. The specimens were corroded in 37 mole% NaCl and 63 mole% Na2SO4 salt mixture at 1000℃ up to 60 min. SiO2 layer was formed on SiC and then this oxide layer was dissolved by Na2O ion in the salt mixture. The rate of corrosion of the specimen containing 10 wt% Al2O3 was slower than that of the specimen containing 2 wt% Al2O3. This is due to the presence of continuous grain boundary phase in the specimen containing 10 wt% Al2O3. The oxidation of SiC produced gas bubbles at the SiC-SiO2 interface. The rate of corrosion follows a linear rate law up to 50 min. and then was accelerated. This acceleration is due to the disruption oxide layer by the gas evolution at SiC-SiO2 interface. Pitting corrosion has found at open pores and grain boundaries.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.340-340
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• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.214-217
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• 2003

In this study, we prepared ZnO thin film on $SiO_2$/Si substrate by FTS (Facing Targets Sputtering) apparatus which can reduce damage on the thin film because the bombardment of high-energy Particles such as ${\gamma}$-electron can be restrained. And, properties of thin filnl grown with ZnO buffer-layer which can be suppress initial growth layer was investigated. The crystalline and the c-axis preferred orientation of ZnO thin film was also investigated by XRD. As a result, we noticed that the ZnO thin film has a good crystallographic characteristic at thickness of ZnO buffer layer 10, 20 nm and working pressure 1 mTorr.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.2
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• pp.177-184
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• 1996

We adopted the $Pt/SiO_{2}/Si$ and the $Ir/SiO_{2}/Si$ substrates of which buffer layer is $PbTiO_{3}$ to improve electrode and interfacial properties of PZT thin film deposited by reactive sputtering method using metal target in this study. We got PZT thin film to have highly oriented(100) structure and good crystallinity using buffer layer in Pt bottom-electrode, though randomly oriented PZT thin film was obtained without buffer layer. Although great improvement of PZT phase formation on Ir bottom-electrode with buffer layer was not observed, we observed the increase of remennant polarization and the decrease of coercive field compared with properties of PZT thin films on the Pt bottom-electrode. So we got the results of the increase of dielectric constant using buffer layer on fabrication of PZT thin film and the better dielectric properties in PZT thin film using Ir bottom-electrode compared with that using Pt bottom-electrode.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.47-52
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• 2008

As the packing density of IC devices gets ever higher, the thickness of the gate $SiO_2$ layer of the MOS devices is now required to be reduced down to 1 nm. For such a thin $SiO_2$ layer, the MOS device cannot operate properly because of tunneling current and threshold voltage shift. Hence there has been much effort to develop new dielectric materials which have higher dielectric constants than $SiO_2$ and is free from such undesirable effects. In this work, the physical and electrical characteristics of ALD $ZrO_2$ film have been studied. After deposition of a thin ALD $ZrO_2$ film, it went through thermal treatment in the presence of argon gas at $800^{\circ}C$ for 1 hr. The characteristics of morphology, crystallization kinetics, and interfacial layer of $Pt/ZrO_2/Si$ samples have been investigated by using the analyzing instruments like XRD, TEM and C-V plots. It has been found that the characteristics of the $Pt/ZrO_2/Si$ device was enhanced by the thermal treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.