• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.85-85
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• 1999

Pb(Mg1/3Nb2/3)O3-PbTiO3 (PMN-PT)는 높은 유전율로 인해 강유전체 메모리 소자의 응용을 위한 연구가 되고 있으며 또한 전왜(electrostrictive)성을 갖고 있어 이력현상을 갖지 않음으로 최근 들어 미세전기기계소자(MEMS)로의 연구가 활발히 되고 있다. 본 연구에서는 MEMS 소자로서의 응용을 위해 저응력 SiNx가 형성된 Si 기판위에 Pt 전극 혹은 산화물 전극 SrRuO3를 갖는 PMN-PT 박막 캐패시터를 제조하였다. 박막 하부의 구조는 금속전극의 경우 Pt/Ti/LTO/SiNx/Si이고 산화물전극은 SrRuO3/Ru/SiNx/Si의 구조를 갖는다. PMN-PT 박막은 alkoxide를 기반으로 회전 coating 방법을 사용하여 박막 하부층의 변화를 주어서 성장시켰다. PMN-PT 용액의 합성은 분말합성법에서 사용하는 columbite 방법을 응용하여 상대적으로 반응정도가 낮은 Mg를 Nb와 우선 반응하여 Mg-Nb solution을 얻고 Pb-acetate 용액과 합성하여 PMN을 제조한 후 PT를 반응시켜서 제조하였다. PMN-PT 박막에서 동일한 공정조건 하에서 박막 하부층의 구조에 따라서 PMN-PT 박막의 조성이 A2B2O6의 조성을 가지는 파이로클러어상이 형성되거나 또는 ABO3인 페로브스카이트상이 형성되는 것을 관찰하였다. 금속 전극인 Pt를 하부전극으로 사용한 경우는 혼재상이 형성되어 패로브스카이드 PMN-PT를 얻기 위해 seed layer로서 PbTiO3를 사용하였으며 이러한 seed layer 위에 형성된 PMN-PT를 형성하는 경우 rutile 구조인 RuO2 위에 성장시킨 PMN-PT는 파이로클로어와 페로브스카이트의 혼재상이 얻어졌으나 pseudo-perovskite 구조인 SrRuO3 박막 위에 형성된 PMN-PT 박막에서는 페로브스카이트가 주된 상으로 얻어졌다. 즉 하부층(전극 또는 seed layer)으로 perovskite 구조를 갖는 박막을 형성하게 되면 페로브스카이트를 갖는 PMN-PT 박막을 얻을 수 있었다. 전기적인 특성은 상부전극으로 Pt를 사용하여 HP 4194A로 측정을 하였다. PT seed layer를 포함한 PMN-PT 박막은 유전상수 1086과 유전손실 2.75%을 가졌다.

• Corrosion Science and Technology
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• v.5 no.2
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• pp.77-83
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• 2006

The plasma electrolytic oxidation (PEO) process is a relatively new surface treatment technique that produces a chemically stable and environment-friendly electrolytic coating that can be applied to all types of magnesium alloys. In this study, the characteristics of oxide film were examined after coating the extruded AZ31 alloy through the PEO process. Hard ceramic coatings were obtained on the AZ31 alloy by changing the coating time from 10min to 60min. The morphologies of the surface and the cross-section of the PEO coatings were examined by scanning electron microscopy and optical microscopy, and the thickness of the coating was measured. The X-ray diffraction pattern of the coating shows that the coated layer consists mainly of the MgO and $Mg_2SiO_4$ phases after the oxidation reaction. The hardness of the coated AZ31 alloy increased with increasing coating time. In addition, the corrosion rates of the coated and uncoated AZ31 alloys were examined by salt spray tests according to ASTM B 117 and the results show that the corrosion resistance of the coated AZ31 alloy was superior to that of the un-coated AZ31 alloy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.65-66
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• 1994

This paper describes study on the preparation of ferrite powder for bonded mallets. The specimen which has the basic composition of SrO$.$nF$_2$O$_3$ with n=5.9 is in nonstoichiomatric region. Calcination is performed under N$_2$ atmosphere 1175$^{\circ}C$, 1200$^{\circ}C$, 1225$^{\circ}C$, 1250$^{\circ}C$ and 1275$^{\circ}C$ respectively. Then, Cooling is carried out in the furnace. In order to increase coecivity and obtain uniform grain size, we add to the specimen 0.7wt%CaCO$_3$, 0.3wt % SiO$_2$, 0.5wt%Na$_2$SiO$_3$ and 0.5wr% Al$_2$O$_3$. Also, in order to increase milling effect, carbon coating on sample particles is tried. As the result, single magnetic domain partic1e with Size of 1$\mu\textrm{m}$ in obtained and magnetic properties are improved.

• Bulletin of the Korean Chemical Society
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• v.30 no.3
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• pp.653-656
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• 2009

3-Dimensionally ordered macroporous $LiMn_2O_4$ thin film was prepared by a sol-gel and dip coating method on Pt/Ti/$SiO_2$/Si substrate. An opal structure consisting of mono dispersed polystyrene beads (300 nm) was used as a template. After solution containing Mn and Li precursors was coated on the template-deposited substrate, the template and organic materials in the precursors was removed by calcination at 400 ${^{\circ}C}$. And then the 3-dimensional $LiMn_2O_4$ thin film with spinel structure was fabricated by heat treatment at 700 ${^{\circ}C}$. The structural and electrochemical property was investigated by XRD, SEM and charge-discharge cycler.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.660-663
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• 2001

The devices of BST thin films to composite (Ba$\_$0.7/ Sr$\_$0.3/)TiO$_3$using sol-gel method were fabricated by changing of the depositing layer number on Pt/Ti/SiO$_2$/Si substrate. The thin film capacitor to be ferroelectric devices was investigated by structural and electrical properties. The thickness of BST thin films at each coating numbers 3, 4 and 5 times was 2500[${\AA}$], 3500[${\AA}$], 3800[${\AA}$]. The dielectric factor of thin film when the coating numbers were 3, 4 and 5 times was 190, 400 and 460 on frequency 1[MHz]. The dielectric loss of BST thin film was linearly increased by increasing of the specimen area.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.414-414
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• 2009

나노스피어 리소그래피는 기존의 리소그래피 방법에 비해 나노 크기 패턴을 제작하는데 공정이 간단하며 재현성있게 대면적에 패터닝이 가능하다는 장점이 있다. 본 연구에서는 Vertical LED(V-LED)의 External quantum efficiency 향상을 위하여 나노스피어 리소그래 피를 이용하여 V-LED의 n-GaN 표면을 패터닝을 하였다. n-GaN 위에 Sputter를 이용하여 $SiO_2$를 증착 후 나노스피어를 스핀 코팅을 이용하여 단일막을 형성하였다. 그 후, 반응성 이온 식각 장치를 이용하여 나노스피어의 크기를 조절하고 $SiO_2$층을 식각하였다. 다음과 같은 공정 후 $SiO_2$층을 Mask층으로 하여 n-GaN 표면을 식각하였다. 실험 결과 나노스피어 리소그래피를 이용하여 V-LED의 External quantum efficiency 향상을 위한 n-GaN 표면의 패턴 제작이 가능함을 확인할 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.55.1-55.1
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• 2009

나노 임프린트 리소그래피 기술은 고집적된 나노 구조물을 경제적으로 형성시킬 수 있는 유망한 차세대 리소그래피 기술 중 하나로써 광학 소자 뿐만 아니라 반도체, 디스플레이, 바이오 소자 등 다양한 분야에 적용이 가능하다. 본 연구에서는 태양전지 보호층으로 사용되는 유리 기판의 투과도 향상을 위해 나노 크기의 패턴을 형성하여 표면 반사를 최소화 하였으며, 보호층의 유지보수 부담을 줄이기 위해 패턴 표면에 방오 기능을 갖는 hydrophobic SAM(Self Assembled Mono-layer)을 형성하였다. 또한, SAM coated nano-sized pattern 형성을 위해 사용 된 $SiO_2$ 증착층과 SAM이 투과도에 끼치는 영향을 확인하기 위하여 bare glass, $SiO_2$ deposited glass, SAM coated glass 그리고 SAM/$SiO_2$ coated glass를 제작하였으며, 각각의 투과도를 측정하여 비교 분석 하였다. 투과도를 측정하기 위해 UV-Vis spectrophotometer를 사용하였으며, 방오 기능을 측정하기 위해 접촉각 측정장치를 사용하였다. 접촉각의 측정을 통해 이형처리(SAM coating)를 한 기판 표면이 소수성으로 바뀌어 물이나 먼지가 잘 묻지 않게 되는 것을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.45-48
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• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.73-79
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• 2013

Crystalline silicon solar cells with $SiN_x/SiN_x$ and $SiN_x/SiO_x$ double layer anti-reflection coatings(ARC) were studied in this paper. Optimizing passivation effect and optical properties of $SiN_x$ and $SiO_x$ layer deposited by PECVD was performed prior to double layer application. When the refractive index (n) of silicon nitride was varied in range of 1.9~2.3, silicon wafer deposited with silicon nitride layer of 80 nm thickness and n= 2.2 showed the effective lifetime of $1,370{\mu}m$. Silicon nitride with n= 1.9 had the smallest extinction coefficient among these conditions. Silicon oxide layer with 110 nm thickness and n= 1.46 showed the extinction coefficient spectrum near to zero in the 300~1,100 nm region, similar to silicon nitride with n= 1.9. Thus silicon nitride with n= 1.9 and silicon oxide with n= 1.46 would be proper as the upper ARC layer with low extinction coefficient, and silicon nitride with n=2.2 as the lower layer with good passivation effect. As a result, the double layer AR coated silicon wafer showed lower surface reflection and so more light absorption, compared with $SiN_x$ single layer. With the completed solar cell with $SiN_x/SiN_x$ of n= 2.2/1.9 and $SiN_x/SiO_x$ of n= 2.2/1.46, the electrical characteristics was improved as ${\Delta}V_{oc}$= 3.7 mV, ${\Delta}_{sc}=0.11mA/cm^2$ and ${\Delta}V_{oc}$=5.2 mV, ${\Delta}J_{sc}=0.23mA/cm^2$, respectively. It led to the efficiency improvement as 0.1% and 0.23%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.132-135
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• 1999

Recently, the ceramics of high permittivity are applied to DRAM and FRAM. In this study, (B $a_{x}$ S $r_{l-x}$)Ti $O_3$(BST) ceramics thin films were prepared by Sol-Gel method. BST solution was made and spin-coated on Pt/ $SiO_2$/Si substrate at 4000 [rpm] for 10 seconds. Coated specimens were dried at 150[$^{\circ}C$] for 5 minutes. Coating process was repeated 3 times and then sintered at 750[$^{\circ}C$] for 30 minutes. Each specimen was analyzed structure and electrical characteristics. Thickness of BST ceramics thin films are about 2000($\AA$). Dielectric constant and loss of thin films was little decreased at 1[KHz] ~1[KHz]. Dielectric constant and loss to frequency were 250 and 0.02 in $Ba_{0.7}$S $r_{0.3}$Ti $O_3$. The properly of leakage current as the realation between the current and the voltage was that change of the leakage current was stable when the applied voltage was 0~3[V].