• Journal of the Korean institute of surface engineering
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• v.41 no.5
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• pp.189-193
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• 2008

In this study, we carried out an investigation of the etching characteristics (etch rate, selectivity to $SiO_2$ and $HfO_2$) of TiN thin films in the $CH_4$/Ar inductively coupled plasma. The maximum etch rate of $274\;{\AA}/min$ for TiN thin films was obtained at $CH_4$(80%)/Ar(20%) gas mixing ratio. At the same time, the etch rate was measured as function of the etching parameters such as RF power, Bias power, and process pressure. The X-ray photoelectron spectroscopy analysis showed an efficient destruction of the oxide bonds by the ion bombardment as well as showed an accumulation of low volatile reaction products on the etched surface. Based on these data, the ion-assisted chemical reaction was proposed as the main etch mechanism for the $CH_4$ containing plasmas.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.88-92
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• 2023

The ferroelectricity in Hf_0.5Zr_0.5O₂ (HZO) thin films is one of the most interesting topics for next-generation nonvolatile memory applications. It is known that a crystallization process is required at a temperature of 400℃ or higher to form an orthorhombic phase that results in the ferroelectric properties of the HZO film. However, to realize the integration of ferroelectric HZO films in the back-end-of-line, it is necessary to reduce the annealing temperature below 400℃. This study aims to comprehensively analyze the ferroelectric properties according to the annealing temperature (350-500℃) and time (1-5 h) using a furnace as a crystallization method for HZO films. As a result, the ferroelectric behaviors of the HZO films were achieved at a temperature of 400℃ or higher regardless of the annealing time. At the annealing temperature of 350℃, the ferroelectric properties appeared only when the annealing time was sufficiently increased (4 h or more). Based on these results, it was experimentally confirmed that the optimization of the annealing temperature and time is very important for the ferroelectric phase crystallization of HZO films and the improvement of their ferroelectric properties.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.339-339
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• 2012

지난 몇 년 동안, 투명 비정질 산화물 반도체는 유기 발광 다이오드, 플렉서블 전자 소자, 솔라 셀, 바이오 센서 등 많은 응용분야에 연구되고 있다. 투명 비정질 산화물 반도체 그룹들 중, 특히 비정질 IGZO 박막 트랜지스터는 비정질 상태임에도 불구하고 높은 이동도와 낮은 동작 전압으로 훌륭한 소자 특성을 보인다. 이러한 고성능의 IGZO 박막 트랜지스터는 RF 마그네트론 스퍼터링이나 pulsed laser deposition과 같은 고진공 장비를 이용하여 이미 여러 그룹에서 제작되고 발표되었다. 하지만 진공 증착 시스템은 제조 비용의 절감이나 디스플레이 패널의 대면적화에 큰 걸림돌이 되고 있고, 이러한 문제점을 극복하기 위해서 용액 공정은 하나의 해결책이 될 수 있다. 용액 공정의 가장 큰 장점으로는 저온 공정이 가능하기 때문에 글라스나 플라스틱 기판에서 대면적으로 제작할 수 있고 진공 장비가 필요없기 때문에 제조 비용을 획기적으로 절감시킬 수 있다. 본 연구에서는 high-k 게이트 절연막과 IGZO 채널 층을 용액 공정을 이용하여 박막 트랜지스터를 제작하고 그에 따른 전기적 특성을 분석하였다. IGZO의 몰 비율은 In, Ga, Zn 순으로 각각 0.2 mol, 0.1 mol, 0.1 mol로 제작하였고, high-k 게이트 절연막으로는 Al2O3, HfO2, ZrO2을 제작하였다. 또한, 용액 공정 IGZO TFT를 제작하기 전, 용액 공정 high-k 게이트 절연막 캐패시터를 제작하여 그 특성을 분석하였다. 다양한 용액 공정 high-k 게이트 절연막 중, 용액공정 HfO2를 이용한 IGZO TFT는 228.3 [mV/dec]의 subthreshold swing, 18.5 [$cm^2/V{\cdot}s$]의 유효 전계 이동도, $4.73{\times}106$의 온/오프 비율을 보여 매우 뛰어난 전기적 특성을 확인하였다.

• Korean Journal of Materials Research
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• v.17 no.5
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• pp.273-277
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• 2007

Vertically aligned Zinc Oxide rod arrays were grown by the self-assembly hydrothermal process on the GaN epitaxial layer which has a same lattice structure with ZnO. Zinc nitrate and DETA solutions are used in the hydrothermal process. The $(HfO_2)$ thin film was deposited on GaN and the patterning was made by the photolithography technique. The selective growth of ZnO rod was achieved with the patterned GaN substrate. The fabricated ZnO rods are single crystal, and have grown along hexagonal c-axis direction of (002) which is the same growth orientation of GaN epitaxial layer. The density and the size of ZnO rod can be controlled by the pattern. The optical property of ordered array of vertical ZnO rods will be discussed in the present work.

• Korean Journal of Materials Research
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• v.8 no.9
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• pp.837-842
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• 1998

As the size of the integrated circuit is scaled down the importance of Si cleaning has been emphasized. One of the major concerns is abut the removal of metallic impurities such as Cu and Fe on Si surface. In this study, we intentionally contaminated Cu and Fe on the Si wafers and cleaned the wafer by cleaning splits of the chemical mixture of $\textrm{H}_2\textrm{O}_2$ and HF and the combination of HF treatment with UV/$\textrm{O}_3$ treatment. The contamination level was monitored by TXRF. Surface microroughness of the Si wafers was measured by AFM. The Si wafer surface was examined by SEM. AES analysis was carried out to analyze the chemical composition of Cu impurities. The amount of Cu impurities after intentional contamination was abut the level of $\textrm{10}^{14}$ atoms/$\textrm{cm}^2$. The amount of Cu was decreased down to the level of $\textrm{10}^{10}$ atoms/$\textrm{cm}^2$ by cleaning splits. The repeated treatment exhibited better Cu removal efficiency. The surface roughness caused by contamination and removal of Cu was improved by repeated treatment of the cleaning splits. Cu were adsorbed on Si surface not in a thin film type but in a particle type and its diameter was abut 100-400${\AA}$ and its height was 30-100${\AA}$. Cu was contaminated on Si surface by chemical adsorption. In the case of Fe the contamination level was $\textrm{10}^{13}$ atoms/$\textrm{cm}^2$ and showed similar results of above Cu cleaning. Fe was contaminated on Si surface by physical adsorption and as a particle type.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.181.1-181.1
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• 2015

용액 공정을 이용한 Resistive random access memory (ReRAM)은 간단한 공정 과정, 대면적화, 저렴한 가격 등의 장점으로 인해 큰 관심을 받고 있으며, HfOx, TiOx, AlOx 등의 산화물이 ReRAM 절연 막으로 주로 연구되고 있다. 더 나아가 최근에는 organic 물질을 메모리 소자로 사용한 연구가 보고되고 있다. 이는 경제적이며, wearable 또는 flexible system에 적용이 용이하다. 그럼에도 불구하고, organic 물질을 갖는 메모리 소자는 기존의 산화물 소자에 비해 열에 취약하며 전기적인 특성과 신뢰성이 우수하지 못하다는 단점을 가지고 있다. 이를 위한 방안으로 본 연구에서는 AlOx - polymethylmethacrylate (PMMA) blended thin film ReRAM을 제안하였다. 이는 organic물질의 전기적 특성을 개선시킬 뿐 아니라, inorganic 물질을 wearable 소자에 적용했을 때 발생하는 crack과 같은 기계적 물리적 결함을 해결할 수 있는 새로운 방법이다. 먼저, P-type Si 위에 습식산화를 통하여 SiO2 300 nm 성장시킨 기판을 사용하여 electron beam evaporation으로 10 nm의 Ti, 100 nm의 Pt 층을 차례로 증착하였다. 그리고 PMMA 용액과 AlOx 용액을 초음파를 이용하여 혼합한 뒤, 이 용액을 Pt 하부 전극 상에서 spin coating방법으로 1000 rpm 10초, 5000 rpm 30초의 조건으로 증착하였다. Solvent 및 불순물 제거를 위하여 150, 180, $210^{\circ}C$의 온도로 30 분 동안 열처리를 진행하였고, shadow mask를 이용하여 상부 전극인 Ti를 sputtering 방식으로 100 nm 증착하였다. 150, 180, $210^{\circ}C$로 각각 열처리한 AlOx - PMMA blended ReRAM의 전기적 특성은 HP 4156B semiconductor parameter analyzer를 이용하여 측정하였다. 측정 결과 제작된 소자 전부에서 2 V이하의 낮은 동작전압, 안정된 DC endurance (>150cycles), 102 이상의 높은 on/off ratio를 확인하였고, 그 중 $180^{\circ}C$에서 열처리한 ReRAM은 더 높은 on/off ratio를 갖는 것을 확인하였다. 결론적으로 baking 온도를 최적화하였으며 AlOx - PMMA blended film ReRAM의 우수한 메모리 특성을 확인하였다. AlOx-PMMA blended film ReRAM은 organic과 inorganic의 장점을 갖는 wearable 및 system용 비휘발성 메모리소자에 적용이 가능한 경제적인 기술로 판단된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.323-324
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• 2007

Investigation of improving the properties of UV photodetector which uses the wide bandgap of ZnO are under active progress. In this paper, transparent conducting aluminum-doped Zinc oxide films(AZO) were prepared by rf magnetron sputtering on glass(corning 1737) and p-Si substrate, were then annealed at temperature $400^{\circ}C$ for 2hr. The AZO thin films were deposited by RF sputtering system. HF power and work pressure is 120 W and 15 mTorr, respectively, and the purity of AZO target is 5N. The AZO thin films were deposited at 300, 400, $500^{\circ}C$, and $600^{\circ}C$. For sample deposited at $400^{\circ}C$, we observed best $V_r-I_{ph}$ of 0.94 mA and good transmittance.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.161.1-161.1
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• 2016

박막 태양전지의 광 산란을 위한 텍스쳐 된 표면은 반사 손실을 감소시키기 위한 것이다. 그러나, 투명한 전극(TCO)의 텍스쳐 된 표면은 빛의 가용성을 제한하고, 장파장 영역에서 haze의 수치를 감소시키며, 전반사의 증가는 박막 태양전지의 Jsc를 감소시킨다. 본 논문에서는 높은 빛의 가용성을 위하여 HF+HCl 혼합용액을 이용하여 표면의 질을 향상시키기 위한 해결책을 제시했다. 같은 HF+HCl 혼합용액을 사용하여, 540 nm의 파장에서 약 85 %의 높은 haze 수치를 달성했으며, ZnO:Al 막의 증착 후에 식각된 유리 기판과 함께 비교했을 때, 2.3%의 haze 수치의 감소를 얻었다. 또, 깊은 습식 식각에 의하여 Haze 수치를 증가시키기 위한 메커니즘 간단히 설명했다. 텍스쳐 된 유리 기판의 haze 수치의 측면에서 광학 이득은 일반적인 Asahi FTO 유리(${\lambda}=540nm$의 13.5%)에 비해 상당히 높다. 이러한 높은 haze 수치의 AZO 박막은 박막 태양전지의 Jsc를 개선하는데 이용할 수 있다.