• Communications of Mathematical Education
• /
• v.19 no.4 s.24
• /
• pp.633-647
• /
• 2005

The rapid change in school mathematics curricula occurred over last some periods requires lots of change or improvement in the education method for the university mathematics, especially in calculus. As an effort in this direction we restrict our concern to the freshmen of year 2002 of the Korea university of technology and education to investigate a correlation between their mathematics score on the national entrance examination and achievement score measured by their final grades in a calculus course. As a result of this research we propose a step-wise level educational model for the calculus education. In the model an appropriate teaching contents and method proceeding through the three steps are suggested and implementation issues are discussed. We believe that carrying out mathematics curricular are suggested in the model will be of service to calculus education particularly for student under the 7th national curriculum reform.

• Journal of computational fluids engineering
• /
• v.3 no.1
• /
• pp.11-21
• /
• 1998

A vorticity-based method for the numerical solution of the two-dimensional incompressible Navier-Stokes equations is presented. The governing equations for vorticity, velocity and pressure variables are expressed in an integro-differential form. The global coupling between the vorticity and the pressure boundary conditions is fully considered in an iterative procedure when numerical schemes are employed. The finite volume method of the second order TVD scheme is implemented to integrate the vorticity transport equation with the dynamic vorticity boundary condition. The velocity field is obtained by using the Biot-Savart integral. The Green's scalar identity is used to solve the total pressure in an integral approach similar to the surface panel methods which have been well established for potential flow analysis. The present formulation is validated by comparison with data from the literature for the two-dimensional cavity flow driven by shear in a square cavity. We take two types of the cavity now: (ⅰ) driven by non-uniform shear on top lid and body forces for which the exact solution exists, and (ⅱ) driven only by uniform shear (of the classical type).

• The Transactions of the Korean Institute of Power Electronics
• /
• v.4 no.3
• /
• pp.231-239
• /
• 1999

An improved version of current-regulated delta modulator (CRDM) is investigated for the output cunent control of v voltage-source inverters that have transformer-coupled series resonant load and are operated at the resonant frequency. Conventional CRDM has not only CUlTent offset problem but also transformer flux saturation problem when i it is applied to induction heating systems that have transformel-coupled loads. To cope with these problems, the effect of flux saturation is analysed, and simple method to av이d the problem is proposed. And integral type of CRDM is a adopted to remove the cunent offset. The boundaries of integrator gain for stable operation is calculated using the c concept of sliding mode controL The validity of proposed strategy is vel퍼ed through simulations and prototype e experiments.

• Journal of Ocean Engineering and Technology
• /
• v.9 no.2
• /
• pp.98-111
• /
• 1995

High temperature low cycle fatigue shows that cycle-dependent crack growth owing to cyclic plastic deformation occurred simultaneosly with time-dependent crack growth owing to intergranular deformation. Consequently, to estimate crack growth rate uniquely, many to investigators have proposed various kinds of parameters and theories but these could not produce satisfactory results. Therefore the goal of this study is focused on prediction of crack growth rate using predominant damage rule, linear cumulative damage rule and transitional parameter ${\Delta}J_c/{\Delta}J_f$. On the basis of these sinusoidal loading waveform at 600$^{\circ}C$ and 700$^{\circ}C$.

• Journal of the Korean Society for Precision Engineering
• /
• v.15 no.1
• /
• pp.43-50
• /
• 1998

The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.7
• /
• pp.106-112
• /
• 2000

The purpose of this paper is to study on the control of the engine idle speed under sudden A/C load which is one of the most severe disturbances on engines. Three types of the closed-loop controller are developed for the stable engine idle speed control. The input of the controller is an error of rpm. The output of the controller is an ISCV duty cycle. The anticipation delay is considered to deal with the delay time of the air mass in engine. The PID, Fuzzy and PID-type Fuzzy controllers with the anticipation delay have improved the engine idle speed condition more than current ECU map table under the A/C load.

• Proceedings of the KIPE Conference
• /
• 2020.08a
• /
• pp.196-198
• /
• 2020

본 논문은 SiC MOSFET의 단락 검출을 위한 고정밀 Rogowski 코일 회로 설계 방법을 제안한다. 설계 방법을 제안하기 위해 먼저 Rogowski 코일의 기본 구성인 적분기를 실제 시스템 요구 사양에 맞추어 설계한다. 설계한 회로의 성능 확인을 위하여 DPT (double pulse test)를 실시하며, test 결과 분석을 통해 문제점을 파악하고 전류 센싱 정밀도 향상을 위해 입출력 필터 설계 및 Rogowski 코일 턴 수를 변경한다. 변경한 각 조건들에 대하여 DPT를 진행하고 각 test 결과를 기반으로 Rogowski 코일 회로 설계 방안을 제안한다.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.5
• /
• pp.51-57
• /
• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.39 no.7
• /
• pp.645-652
• /
• 2015

In this study, a method for determining Ramberg-Osgood constants for leak-before-break evaluation was investigated. The Ramberg-Osgood constants were calculated for SA312, TP316, and SA-508 Gr.1a in an operating temperature of $316^{\circ}C$. Incremental plasticity, using stress-strain data obtained from experiment, and deformation plasticity, using the Ramberg-Osgood constants, were considered in a finite element analysis. Using incremental plasticity and deformation plasticity, J-integrals and crack opening displacement values were calculated and compared. By comparing the results of incremental plasticity and deformation plasticity, a suitable method for determining Ramberg-Osgood constants for leak-before-break evaluation was confirmed.

• Journal of Korea Multimedia Society
• /
• v.14 no.3
• /
• pp.368-377
• /
• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.