• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.16-20
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• 1988

This paper presents a new algorithm for solving the inverse kinematics in real-time applications. The end-tip movement of each link can be resolved into the basic resolution unit, .DELTA.l, which depends on link length, reduction ratio and resolution of the incremental encoder attached to the joint. When x- and y-axis projection of the end-tip movement are expressed in .DELTA.l unit, projectional increments .DELTA.x and .DELTA.y become -1, 0 or I by truncation. By using the incremental computation with these ternary value and some simple logic rules, a coordinate transformation can be realized. Through this approach, it should be noted that the floating-point arithmetic and the manipulation of trigonometric functions are completely eliminated. This paper demonstrates the proposed method in a parallelogram linkage type, two-link arm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1579-1589
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• 1997

This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.10
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• pp.513-519
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• 2001

This paper proposed a random sigma-delta modulator(RSDM), which is constructed by a 1st order sigma-delta modulator(SDM) and a simple structured random binary generator(RBG). The 1st order SDM produces a switching pulse waveform which has the same low-frequency component as the reference input, while the RBG spreads the distribution of the number of sampling per switching cycle, and thus disperses the spectrum spikes in the output. The relationship between the harmonic spectra and the number of sampling per switching cycle is studied through computer simulations, and the frequency spectra of the RSDM are confirmed in an experimental setup.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.3
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• pp.31-35
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• 2009

In this paper, tunable 4th order SC(switched capacitor) bandpass ${\sigma}-{\Delta}$(Sigma-Delta) modulator with advanced architecture that can adjust the IF by two coefficient values is proposed for data conversion in the wireless communication. Its architecture can optionally adjust all the 4th order noise transfer function in comparison with the conventional architecture. In order to adjust the IF, the conventional architecture needs the four variable coefficients values, basic clocks and eight clocks. On the other hand, the proposed architecture can adjust the IF by two variable coefficient values and basic clocks only.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.135-139
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• 2008

In this paper, tunable SC(switched capacitor) 2nd order bandpass $\Sigma-\Delta$(Sigma-Delta) modulator with novel architecture that can adjust the IF band center frequency by one coefficient value is proposed for data conversion in the IF(Intermediate Frequency) band. Its architecture can optionally adjust all the 2nd order noise transfer function in comparison with the conventional architecture. In order to adjust the center frequency, the conventional architecture needs the two variable coefficient values, basic clock and eight clocks. On the other hand, the proposed architecture can adjust the center frequency by one variable coefficient value and basic clock only.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1278-1290
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• 2008

This paper proposes a preprocessing method and a neural network based character recognizer to enhance the overall performance of the license plate recognition system. First, plate outlines are extracted by virtual line matching, and then the 4 vertexes are obtained by calculating intersecting points of extracted lines. By these vertexes, plate image is reconstructed as rectangle-shaped image by bilinear transform. Finally, the license plate is recognized by the neural network based classifier which had been trained using delta-bar-delta algorithm. Various license plate images were used in the experiments, and the proposed plate normalization enhanced the recognition performance up to 16 percent.

• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.224-225
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• 2002

펨토초 모드록 레이저는 공진기의 왕복시간 $\tau$마다 펨토초 폭을 갖는 펄스를 발생시키고, Fourier 변환에 의해 주파수 공간에서는 일정한 주파수 간격 $\Delta$ = 1/$\tau$을 가지는 불연속 스펙트럼, 즉 광빗 스펙트럼을 갖게 된다(1). 광빗의 간격, 즉 펄스의 반복률, 은 $\Delta$ ： v$_{g}$l$_{c}$의 관계식에 의해 그룹속도(v$_{g}$)와 공진기 길이(l$_{c}$)에 의해 결정된다. 광빗의 간격을 고정시키기 위한 가장 일반적인 방법은 공진기 길이를 일정하게 유지하는 것이다. (중략)

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.800-807
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• 2006

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.72-76
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• 2004

본 논문에서는 일명 델타변환 무정전전원장치(UPS)로서 알려져 있는 3상 라인 인터랙티브 UPS 시스템의 성능 시험에 대해서 다루고 있다. 델타변환 UPS는 종래의 단일 변환 라인 인터랙티브 UPS 시스템에서 직렬 인덕터를 제거하고 직렬 및 병렬 PWM 컨버터를 사용하는 새로운 라인 인터랙티브 UPS 시스템으로 전원 전류를 직접 제어함으로써 UPS 시스템의 입출력 특성들이 상당히 개선되는 것으로 알려져 있다. 여기서는 UPS 시스템의 성능 시험에서 중요한 내용들인 부하시험, 정전/복전시험, 동기절체 시험 등에 대한 결과들을 제시하고 델타변환 UPS 시스템에 대한 전반적인 평가를 한다.

• Journal of KIISE
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• v.42 no.9
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• pp.1078-1089
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• 2015

In this paper, we propose the Min-hash Assisted Delta-compression Engine(MADE) to improve the lifetime of NAND flash-based storages at the device level. MADE effectively reduces the write traffic to NAND flash through the use of a novel delta compression scheme. The delta compression performance was optimized by introducing min-hash based LSH(Locality Sensitive Hash) and efficiently combining it with our delta compression method. We also developed a delta encoding technique that has functionality equivalent to deduplication and lossless compression. The results of our experiment show that MADE reduces the amount of data written on NAND flash by up to 90%, which is better than a simple combination of deduplication and lossless compression schemes by 12% on average.