• Title/Summary/Keyword: ${\delta}$ filter

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Modeling and Control of a Grid Connected VSI using a Delta Connected LCL Filter ($\Delta$-결선 LCL 필터를 사용하는 삼상 계통 연계 인버터의 모델링과 제어)

  • Lee, Sang-In;Lee, Kui-Jun;Hyun, Dong-Seok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.14 no.1
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    • pp.1-7
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    • 2009
  • There are two ways to connect an LCL filter in a grid-connected VSI. A wye connected LCL filter is general way, and the other is a delta connected LCL filter. While a model of a system with a wye connected LCL filter is calculated, a model of a system with a delta connected LCL filter is not formulated. Thus, we propose a mathematical model of a system with a delta connected LCL filter. Also, a comparative study of capacitor current harmonics of a delta connected LCL filter and a wye connected LCL filter is included. Experimental results exhibit that it is advantageous to control grid currents for a system with a delta connected LCL filter.

Unified FIR filter using delta operator (델타 연산자를 이용한 통합형 FIR 필터)

  • 서민상;권오규
    • 제어로봇시스템학회:학술대회논문집
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    • 1992.10a
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    • pp.912-916
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    • 1992
  • In this paper we investigate the connection between the continuous-time FIR(finite impulse response) filter and the corresponding discrtet-time FIR filter with fast sampling. The interconnection is established by formulating the discrete-time case using delta operators which has superior numerical properties in discretizing prcedure. The aim of this paper is to present a unified FIR filter using the .delta.-operator and to show that, as sampling interval .DELYA. aperator to zero, the results of this filter converge to the corresponding continuous-time reuslts, which implies that the unified FIR filter unifies continous-time FIR filter and discrtet-time FIR filter.

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The Characteristics of $\Delta$-shaped Filter for Full Screen Display on the FPD (FPD상에서 전화면 디스플레이를 위한 $\Delta$-형 필터의 특성)

  • 조화현;최철호;권병헌;최명렬
    • Journal of Korea Multimedia Society
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    • v.3 no.2
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    • pp.184-191
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    • 2000
  • In thid paper, we have analized the characteristics of $\Delta$-shaped filter based on preceeding study. The algorithm of $\Delta$-shaped filter for full screen display has been discussed including their edge-preserving characteristics and computaion complexity compared with the conventional algorithms. PSNR has been employed to compare the proposed method to the conventional algorithms. The proposed algorithm has been implemented using Synopsys VHDL tool. In addition, the features and trade off of the $\Delta$-shaped filter have been discussed.

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Sigma Delta Decimation Filter Design for High Resolution Audio Based on Low Power Techniques (저전력 기법을 사용한 고해상도 오디오용 Sigma Delta Decimation Filter 설계)

  • Au, Huynh Hai;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.11
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    • pp.141-148
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    • 2012
  • A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

MORE GENERAL FORMS OF (∈, ∈ VQk) FUZZY FILTERS OF ORDERED SEMIGROUPS

  • Khan, Asghar;Muhammad, Shakoor;Khalaf, Mohammed M.
    • Honam Mathematical Journal
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    • v.39 no.2
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    • pp.199-216
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    • 2017
  • In the paper [Y. B. Jun, B. Davvaz and A. Khan, Filters of ordered semigroups based on the fuzzy points, JIFS 24 (2013) 619-630]. Jun et al. discussed the notion of (${\in},{\in}{\vee}q_k$)-fuzzy left (resp., right) filters as a generalization of the notion of (${\in},{\in}{\vee}q$)-fuzzy left (resp., right) filters of ordered semigroups. In this article, we try to obtain a more general form that (${\in},{\in}{\vee}q_k$)-fuzzy left (resp., right) filters in ordered semigroups. The notion of (${\in},{\in}{\vee}q_k^{\delta}$)-fuzzy left (resp., right) filters is discussed, and several properties are investigated. Characterizations of an (${\in},{\in}{\vee}q_k^{\delta}$)-fuzzy left (resp., right) filter are established. A condition for an (${\in},{\in}{\vee}q_k^{\delta}$)-fuzzy left (resp., right) filter to be a fuzzy left (resp., right) filter is provided. The important achievement of the study with an (${\in},{\in}{\vee}q_k^{\delta}$)-fuzzy left (right) filter is that the notion of an (${\in},{\in}{\vee}q_k$)-fuzzy left ( right) filter and hence an (${\in},{\in}{\vee}q$)-fuzzy left (resp. right) filter are special cases of an (${\in},{\in}{\vee}q_k^{\delta}$)-fuzzy left (resp. right) filter, and thus several results in published papers are becoming corollaries of our results obtained in this paper.

Design and Analysis of Decimation Filers with Minimal Distortion for a High Speed High Performance Sigma-Delta ADC (고속 고성능 시그마-델타 ADC를 위한 최소왜곡 데시메이션 필터의 설계 및 분석)

  • Kang, Ho-jin;Kim, Hyung-won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2649-2655
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    • 2015
  • While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

A Study on Tuning Factor(δ) and Quality Factor(Q) Values in Design of Single-Tuned Passive Harmonic Filters (단일동조 수동고조파필터 설계시의 동조계수(δ) 및 양호도(Q)값 연구)

  • Cho, Young-Sik;Cha, Han-Ju
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.59 no.1
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    • pp.64-70
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    • 2010
  • This paper presents how to decide on tuning factor(${\delta}$) and quality factor(Q) values in design of single-tuned passive harmonic filters. Tuning factor(${\delta}$) and quality factor(Q) values have to consider before decision on circuit parameters of passive filters. A Study on these two value has not been scarcely performed and only experienced values has been used in passive harmonic filter design by far. As a experienced value, in cases of 5th and 7th filter, tuning factor(${\delta}$) is about 0.94 and 0.96 respectively and quality factor(Q) is, in all cases of, 50. If Single-tuned passive harmonic filter will be off-tuned, performance of filter will be decreased steeply and occur to parallel resonance between system reactance and filter capacitance. Therefore During the operation, In order not to off-tuning, Filter must be tuned at former order than actual tuning order. This is the same that total impedance of filter must have a reactive impedance. In this paper, Tuning factor(${\delta}$) is decided via example of real system and using the bode-plot and then performance of filters confirmed by filter current absorbtion rate. And Quality factor(Q) decided using the bode plot in example system and then performance of filters confirmed by filter current absorbtion rate also, which makes a calculated filter parameters to satisfy IEEE-519 distortion limits. Finally, Performance of the designed passive harmonic filter using the tuning factor(${\delta}$) and quality factor(Q) values, decided in this paper is verified by experiment and shows that 5th, 7th, 9th, 11th and 13th current harmonic distortions are decreased within IEEE-519 distortion limits, respectively.

Decimation Filter Design and Performance Analysis for a High-Speed Sigma-Delta ADC with Minimal Passband Distortion (최소 왜곡의 통과 대역을 가지는 고속 시그마-델타 ADC용 데시메이션 필터의 설계 및 성능 분석)

  • Kang, Ho-jin;Kim, Hyung-won
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.405-408
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    • 2015
  • While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

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A design of high-linearity low-power contiunous-time filter for post-processing of .SIGMA..DELTA. converters ($\Delta$ 변환기 후단 처리용 고선형 저전력 연속시간 필터의 설계)

  • 홍국태;정현택;손한웅;염왕섭;정강민
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.7
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    • pp.1579-1589
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    • 1997
  • This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.

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Low-power Decimation Filter Structure for Sigma Delta A/D Converters in Cardiac Applications (심장박동기용 시그마 델타 A/D 변환기에서의-저전력 데시메이션 필터 구조)

  • 장영범;양세정;유선국
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.2
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    • pp.111-117
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    • 2004
  • The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15% of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.