• Journal of information and communication convergence engineering
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• v.17 no.1
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• pp.1-7
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• 2019

In this paper, we present the block diagonalization (BD) algorithm for the multiple-user multiple input multiple output (MU-MIMO) $4{\times}4$ system using specific purpose processor (SPP) hardware. Our objective is to improve the single-user MIMO (SU-MIMO) system using the MU-MIMO technology, which is remarkably fast and allows more users to connect simultaneously. To that end, our MU-MIMO precoder uses the BD algorithm to ensure signal integrity when connecting multiple users; but remains accurate and stable. However, a precoder that uses the BD algorithm is computationally complex; therefore, we use an SPP with special functions designed to compute the BD algorithm. The implementation test results show that our SPP computes the BD algorithm faster than the software solution.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.738-742
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• 1996

This paper presents the automatic monitoring system for the small and medium sized manufacturing system. The monitoring system was composed of main controller, network card and monitoring sub controller for the unit machine. PC was used for the main controller and monitoring controller, which has the same hardware with the network card, was developed using Intel 80196 microprocessor.

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.299-306
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• 1999

The ${\mu}$-processor based-controlled system is widely used in railway signaling system. The railway signaling systems are highly required safety and reliability. It is necessary to have a fault-tolerant and fail safe concept in ${\mu}$-processor based railway signaling system. In this paper, several architectures and circuits of fault-tolerant computer system is reviewed. The basic concept of the fault-tolerant computer system will be adapted total self checking, strong fail safe, fault display circuit, logic testing circuit and system switching concepts.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.97-100
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• 2001

A 3-way VLIW multimedia signal processor capable of efficient repeated operations as well as both load/store and type transformations for various data types is presented. It is composed of a 32-bit execution unit that can execute two instructions in parallel, an independent load/store unit and a control unit. The processor is implemented with 0.6${\mu}{\textrm}{m}$ gate array and the results are discussed.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

• Korean Journal of Optics and Photonics
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• v.8 no.5
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• pp.426-430
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• 1997

A signal processor is implemented to verify the possibility of a closed-loop signal processing for the open-loop fiber-optic gyroscope (FOG). As an all-digital implementation of phase tracking scheme, it does analog-to digital conversion of the detector output and signal processing all-digitally thereafter for a noise-immune FOG signal processor. It has a potential of 36-bits resolution in the $2\pi$ range which is best in the number and sets no limit in the magnitude of the phase shift. The new signal processor was tested on an all-fiber gyroscope and turned out to have a resolution of $3\mu$rad(corresponds to 0.74 deg/hr), which is good enough to measure the Earth's rotation rate.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.377-383
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• 2002

An all-digital closed-loop (ADCL) signal processor for an open-loop FOG was developed to replace the analog circuitry of a Digital Phase Tracking (DPT) signal processor with new digital circuitry. When the ADCL signal processor without a stabilizer for fiber phase modulator (FPM) was attached to the FOG, temperature drift of FOG was about 0.26$\mu$rad/$^{\circ}C$, which makes the FOG unusable in medium or higher-grade applications. This drift was due to variations of phase modulation amplitude and phase delay of the FPM. The stabilizer controls its phase modulation amplitude and phase delay by regulating the ratio of harmonics of the FOG output. Thus, the stabilizer reduces the drift of the FOG to negligible.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.