Transactions on Semiconductor Engineering (반도체공학회 논문지)

The Institute of Semiconductor Engineers (반도체공학회)
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ENOB 8-bit / 49.98dB-SNDR SAR ADC with Auto Zero Calibration Technique for Offset Improvement

Offset 개선을 위해 Auto Zero Calibration 기법을 적용한 8-bit / 49.98dB-SNDR SAR ADC 설계

  • Chae Eun Jung (Department of Electrical and Computer Engineering, Sungkyunkwan University) ;
  • Juwon Oh (Department of Electrical and Computer Engineering, Sungkyunkwan University) ;
  • Young-Gun Pu (Department of Electrical and Computer Engineering, Sungkyunkwan University) ;
  • Kang-Yoon Lee (Department of Electrical and Computer Engineering, Sungkyunkwan University)
  • Received : 2024.05.24
  • Accepted : 2024.08.01
  • Published : 2024.07.31
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Abstract

This paper proposes a circuit utilizing auto zero technology to minimize offset and enhance accuracy in the reference generator and comparator. As evidence, a comparison between pre and post auto zero usage revealed a reduction of approximately 90% in standard deviation. The proposed circuit was implemented using a 55nm CMOS process, with an input frequency of 781.2 Hz. It achieves an Effective Number of Bits (ENOB) of 8.01 bits and a Signal-to-Noise Distortion Ratio (SNDR) of 49.98 dB.

본 논문은 Reference generator 와 Comparator 에서 발생하는 offset 을 최소화하고 정확도를 향상시키기 위해 Auto zero 기술을 활용한 회로를 제안한다. 이에 대한 근거로 Auto zero 사용 전/후를 비교했을 때 약 90% 표준 편차가 줄어드는 결과를 얻을 수 있었다. 제안하는 회로는 55nm CMOS 공정을 사용하였으며, input frequency 는 781.2 Hz, Effective Number of Bits(ENOB) 8.01bit, Signal-to-Noise Distortion Ratio(SNDR)이 49.98dB 을 보여준다.

Keywords

Acknowledgement

본 연구는 2024 년도 산업통상자원부 및 산업기술평가관리원(KEIT) 연구비 지원에 의한 연구임(20016266)

References

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