Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지
DOI QR코드

DOI QR Code

Properties of Cu Pillar Bump Joints during Isothermal Aging

등온 시효 처리에 따른 Cu Pillar Bump 접합부 특성

  • Eun-Su Jang (Department of Advanced Materials Engineering, Chungbuk National University) ;
  • Eun-Chae Noh (Department of Advanced Materials Engineering, Chungbuk National University) ;
  • So-Jeong Na (Welding and Joining R&D Group, Korea Institute of Industrial Technology (KITECH)) ;
  • Jeong-Won Yoon (Department of Advanced Materials Engineering, Chungbuk National University)
  • 장은수 (충북대학교 신소재공학과) ;
  • 노은채 (충북대학교 신소재공학과) ;
  • 나소정 (한국생산기술연구원 뿌리산업기술연구소) ;
  • 윤정원 (충북대학교 신소재공학과)
  • Received : 2024.03.05
  • Accepted : 2024.03.29
  • Published : 2024.03.30
Download PDF
⟨ Previous Next ⟩

Abstract

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

최근 반도체 칩의 소형화 및 고집적화에 따라 미세 피치에 의한 범프 브리지 (bump bridge) 현상이 문제점으로 주목받고 있다. 이에 따라 범프 브리지 현상을 최소화할 수 있는 Cu pillar bump가 미세 피치에 대응하기 위해 반도체 패키지 산업에서 널리 적용되고 있다. 고온의 환경에 노출될 경우, 접합부 계면에 형성되는 금속간화합물(Intermetallic compound, IMC)의 두께가 증가함과 동시에 일부 IMC/Cu 및 IMC 계면 내부에 Kirkendall void가 형성되어 성장하게 된다. IMC의 과도한 성장과 Kirkendall void의 형성 및 성장은 접합부에 대한 기계적 신뢰성을 약화시키기 때문에 이를 제어하는 것이 중요하다. 따라서, 본 연구에서는 CS(Cu+ Sn-1.8Ag Solder) 구조 Cu pillar bump의 등온 시효 처리에 따른 접합부 특성 평가가 수행되었으며 그 결과가 보고되었다.

Keywords

Acknowledgement

이 논문은 2023년도 정부(과학기술정보통신부)의 재원으로 한국연구재단의 지원(No. 2021R1A2C1009714, No. RS-2023-00247545)을 받아 수행된 연구임

References

  1. K. H. K. Frank, J. Lee, F. L. Chien, R. Lee, C. Mao, and J. Lau, "Electromigration performance of Cu pillar bump for flip chip packaging with bump on trace by using thermal compression bonding", 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 6897267, 56-61(2014).
  2. Y. Wang, K. H. Lu, J. lm, and P. S. Ho, "Reliability of Cu pillar bumps for flip-chip packages with ultra low-k dielectrics", 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 5490819, 1404-1410(2010).
  3. M. Y. Kim, S. K. Lim, and T. S. Oh, "Thermal Cycling and High Temperature Storage Reliabilities of the Flip Chip Joints Processed Using Cu Pillar Bumps", J. Microelectron. Packag. Soc., 17(3), 27-32(2010).
  4. M. Gerber, C. Beddingfield, S. O'Connor, M. Yoo, M. J. Lee, D. B. Kang, and S. S. Park, "Next Generation Fine Pitch Cu Pillar Technology - Enabling Next Generation Silicon Nodes", 2011 IEEE 61st electronic components and technology conference (ECTC), 5898576, 613-618(2011).
  5. J. S. Ha, J. P. Jung, and T. S. Oh, "Effects of Intermetallic Compounds Formed during Flip Chip Process on the Interfacial Reactions and Bonding Characteristics", J. Microelectron. Packag. Soc., 19(2), 35(2012).
  6. J. Y. Choi, M. Y. Kim, S. K. Lim, and T. S. Oh, "Flip Chip Process for RF Packages Using Joint Structures of Cu and Sn Bumps", J. Microelectron. Packag. Soc., 67(2009).
  7. G. T. Lim, B. J. Kim, K. W. Lee, M. J. Lee, Y. C. Joo, and Y. B. Park, "Study on the Intermetallic Compound Growth and Interfacial Adhesion Energy of Cu Pillar Bump", J. Microelectron. Packag. Soc., 15(4), 17-24(2008).
  8. J. C. Liao, A. Liao, S. Peng, G. T. Lin, T. Lu, and S. Chen, "Die Bonding with Non-Clean Flux in Fine Pitch Copper Pillar Bump Study and Reliability Performance for 2.5D IC Package", IEEE 66th Electronic Components and Technology Conference (ECTC), 7545664, 1786-1790(2016).
  9. E. C. Noh, H. W. Lee, and J. W. Yoon, "Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging", J. Microelectron. Packag. Soc., 30(3), 1-10(2023).
  10. G. T. Lim, J. H. Lee, B. J. Kim, K. W. Lee, M. J. Lee, Y. C. Joo, and Y. B. Park, "Effect of Thermal Aging on the Intermetallic compound Growth kinetics in the Cu pillar bump", J. Microelectron. Packag. Soc., 14(4), 15-20(2007).
  11. G. T. Lim, B. J. Kim, K. Lee, J. Kim, Y. C. Joo, and Y. B. Park, "Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps", J. Electron. Mater., 38, 2228-2233(2009). https://doi.org/10.1007/s11664-009-0922-0
  12. T. Wang, F. Tung, L. Foo, and V. Dutta, "Studies on a Novel Flip-Chip Interconnect Structure-Pillar Bump", 2001 Proceedings. 51st Electronic Components and Technology Conference (ECTC), 927911, 945-949(2001).
  13. I. N. Jang, J. H. Park, and Y. S. Ahn, "Mechanical Characteristic Evaluation of Sn-Ag-Cu Lead Free Solder Ball Joint on The Pad Geometry", J. Microelectron. Packag. Soc., 17(2), 41-47(2010).
  14. K. S. Kim, S. H. Huh, and K. Suganuma, "Effects of intermetallic compounds on properties of Sn-Ag-Cu lead-free soldered joints", J. Alloys Compd., 226-236(2003).
  15. S. Chada, R. A. Fournelle, W. Laub, and D. Shangguan, "Copper Substrate Dissolution in Eutectic Sn-Ag Solder and Its Effect on Microstructure", J. Electron. Mater., 29, 1214-1221(2000). https://doi.org/10.1007/s11664-000-0015-6
  16. M. H. Jeong, J. M. Kim, S. H. Yoo, C. W. Lee, and Y. B. Park, "Effect of PCB Surface Finishes on Intermetallic Compound Growth Kinetics of Sn-3.0Ag-0.5Cu Solder Bump", J. Microelectron. Packag. Soc., 17(1), 81-88(2010).
  17. S. K. Kang, D. Y. Shih, N.Y. Donald, W. Henderson, T. Gosselin, A. Sarkhel, and W. K. Choi, "Ag3Sn Plate Formation in the Solidification of Near-Ternary", JOM., 55(6), 61-65(2003). https://doi.org/10.1007/s11837-003-0109-8
  18. D. Xie, D. Shangguan, and H. Kroener, "Pad Cratering Evaluation of PCB", APEX., 2722-2750(2010).
  19. M. H. Heo, D. H. Lee, M. S. Jeong, and J. W. Yoon, "Effects of shear test temperatures and conditions on mechanical properties of Sn-Ag flip-chip solder bumps", J Mater Sci Mater Electron., 33(13), 1003-1012(2022). https://doi.org/10.1007/s10854-022-07991-7