전자통신동향분석 (Electronics and Telecommunications Trends)

한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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Complementary FET로 열어가는 반도체 미래 기술

Complementary FET-The Future of the Semiconductor Transistor

  • 김상훈 (차세대반도체소자연구실) ;
  • 이성현 (차세대반도체소자연구실) ;
  • 이왕주 (차세대반도체소자연구실) ;
  • 박정우 (차세대반도체소자연구실) ;
  • 서동우 (소재부품연구본부)
  • S.H. Kim ;
  • S.H. Lee ;
  • W.J. Lee ;
  • J.W. Park ;
  • D.W. Suh
  • 발행 : 2023.12.01
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초록

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

키워드

과제정보

본 연구는 한국전자통신연구원 내부연구과제(기초연구)의 일환으로 수행되었음[23ZB1310 듀플렉스 반도체 아키텍처 원천기술 개발].

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