Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Lightweighted CTS Preconstruction Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time

레지스터 전달 수준 설계단계에서 사전 클럭트리합성 가능여부 판단을 위한 경량화된 클럭트리 재구성 방법

  • Kwon, Nayoung (School of Electronic Engineering, Kyungpook National University) ;
  • Park, Daejin (School of Electronic Engineering, Kyungpook National University)
  • Received : 2022.08.11
  • Accepted : 2022.08.29
  • Published : 2022.10.31
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Abstract

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

application specific integrated circuit (ASIC) 및 system on chip (SoC) 설계 시 디지털 회로는 클럭에 동기화되어 작동한다. 칩 설계 시, place & route (P&R)에서 설계 조건과 타이밍 조건, 클럭의 동기화 여부 등을 고려한다. P&R에서 클럭 경로에 대한 delay를 줄이기 위해, clock tree synthesis (CTS) 기법을 이용한다. 본 논문에서는 사전 클럭트리 합성 가능 여부 판단을 위한 shallow-CTS 알고리즘을 소개한다. 오픈 소스 Parser-Verilog를 사용하여 register transfer level (RTL) 합성가능한 Verilog를 파싱하여, Pre-CTS와 Post-CTS 단계를 진행하고, 가장 긴 clock path와 버퍼 삽입 전후의 표준편차를 비교하여 CTS의 정확도에 대해 분석한다. 본 논문에서 시간 투입이 많이 되는 licensed EDA tool을 사용하여 CTS 결과를 확인하지 않고, RTL 수준에서 사전 클럭 트리 합성 검증 방법을 제공하여 비용 및 시간문제를 감소할 수 있을 것으로 기대된다.

Keywords

Acknowledgement

This study was supported by the BK21 FOUR project funded by the Ministry of Education, Korea (4199990113966, 10%), and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2018R1A6A1A03025109, 10%, NRF-2022R1I1A3069260, 10%) and by Ministry of Science and ICT (2020M3H2A1078119). This work was partly supported by an Institute of Information and communications Technology Planning and Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2021-0-00944, Metamorphic approach of unstructured validation/verification for analyzing binary code, 40%) and (No. 2022-0-00816, OpenAPI-based hw/sw platformfor edge devices and cloud server, integrated with the on-demand code streaming engine powered by AI, 20%) and (No. 2022-0-01170, PIM Semiconductor Design Research Center, 10%). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

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