• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.150-160
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• 1999

This paper presents a new register transfer level synthesis method to overcome the disadvantages of the previous register transfer level synthesis systems. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system and the 8-bit signed multiplier.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.161-169
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• 2011

This paper presents a new register transfer level synthesis methodology for efficient SOC system design. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Journal of the Korea Society of Computer and Information
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• v.8 no.4
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• pp.111-116
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• 2003

We proposed a optimal clock period selection algorithm for low power Register Transfer Level design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the proposed algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm. The experiment result is to set the same result AR and HAL filter on the high level benchmark and to reduce in the case of two pipe stage 10.5% and three pipe stage as many as 33.4%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1442-1450
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• 1999

In this paper, we present an efficient hardware architecture for the frame memory of the MPEG-2 video encoder. Both the total size of internal buffers and the number of logic gates are reduced by the proposed memory map which can provide an effective interface between MPEG-2 video encoder and the external DRAM. Furthermore, the proposed scheme can reduce the DRAM access time. To realize the frame memory hardware,$0.5\mu\textrm{m}$, VTI, vemn5a3 standard cell library is used. VHDL simulator and logic synthesis tool are used for hardware design and RTL (register transfer level) function verification. The frame memory hardware emulator of the proposed architecture is designed for gate-level function verification. It is expected that the proposed frame memory hardware using VHDL can achieve suitable performance for MPEG-2 MP@ML.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.561-562
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• 2008

In this paper, we propose a establishment of system level environment to exploit PC system with SSD (Solid State Disk) by using TLM (Transaction Level Modeling) method with SystemC language. The reason why we choose this modeling method is that it eases RTL (Register Transfer Level) modeling burdens and we can accurately estimate the performance about different architectural changes. Also, it provides simulation speed which is relatively faster than RTL modeling method. The baseline architectural platform we implemented showed that SSD's internal transfer time is a dominant factor, so we need to improve that part and it is expected to be a good simulator to measure the system's overall performance by exploiting SSD's internal architectures.

• Journal of Environmental Health Sciences
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• v.48 no.5
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• pp.272-281
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• 2022

Background: The constant consumption of chemical products owing to expanding industrialization has led to an increase in public interest in chemical substances. As the production and disposal processes for these chemical products cause environmental problems, regional information on the hazard level of chemical substances is required considering their effects on humans and in order to ensure environmental safety. Objectives: This study aimed to identify hazard contribution and spatiotemporal characteristics by region and chemical by calculating a hazard-based result score using pollutant release and transfer register (PRTR) data. Methods: This study calculated the chemical discharge and hazard-based result score from the Risk-Screening Environmental Indicators (RSEI) model, analyzed their spatiotemporal patterns, and identified hotspot areas where chemical discharges and high hazard-based scores were concentrated. The amount of chemical discharge and hazard-based risk scores for 250 cities and counties across South Korea were calculated using PRTR data from 2011 to 2018. Results: The chemical discharge (high densities in Incheon, Daegu, and Busan) and hazard-based result scores (high densities in Incheon, Chungcheongnam-do, and some areas of Gyeongsangnam-do Province) showed varying spatial patterns. The chemical discharge (A, B) and hazard-based result score (C, D) hotspots were identified. Additionally, identification of the hazard-based result scores revealed differences in the type of chemicals contributing to the discharge. Ethylbenzene accounted for ≥80% of the discharged chemicals in the discharge hotspots, while chromium accounted for >90% of the discharged chemicals in the hazard-based result score hotspots. Conclusions: The RSEI hazard-based result score is a quantitative indicator that considers the degree of impact on human health as a toxicity-weighted value. It can be used for the management of industries discharging chemical substances as well as local environmental health management.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.

• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.