Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer

진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구

  • Yeon, Ji-Yeong (School of Electronics Engineering, Chungbuk National University) ;
  • Lee, Khwang-Sun (School of Electronics Engineering, Chungbuk National University) ;
  • Yoon, Sung-Su (School of Electronics Engineering, Chungbuk National University) ;
  • Yeon, Ju-Won (School of Electronics Engineering, Chungbuk National University) ;
  • Bae, Hagyoul (Department of Electronic Engineering, Jeonbuk National University) ;
  • Park, Jun-Young (School of Electronics Engineering, Chungbuk National University)
  • Received : 2022.06.24
  • Accepted : 2022.08.18
  • Published : 2022.11.01
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Abstract

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

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Acknowledgement

이 성과는 정부(과학기술정보통신부)의 재원으로 한국연구재단의 지원을 받아 수행된 연구임 (No. 2022R1F1A1071914 and 2021R1F1A1049456).

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