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벌크 실리콘 기판을 이용한 삼차원 선택적 산화 방식의 핀 채널 MOSFET

Three-Dimensional Selective Oxidation Fin Channel MOSFET Based on Bulk Silicon Wafer

  • 조영균 (공주대학교, 전기전자제어공학부) ;
  • 남재원 (서울과학기술대학교 전자IT미디어공학과)
  • Cho, Young-Kyun (Division of Electrical, Electronic and Control Engineering, Kongju National University) ;
  • Nam, Jae-Won (Department of Electronic Engineering, SeoulTech)
  • 투고 : 2021.09.09
  • 심사 : 2021.11.20
  • 발행 : 2021.11.28

초록

본 삼차원 선택적 산화를 이용하여 20 nm 수준의 핀 폭과 점진적으로 증가된 소스/드레인 확장 영역을 갖는 핀 채널을 벌크 실리콘 기판에 제작하였다. 제안된 기법을 이용하여 삼차원 소자를 제작하기 위한 공정기법 및 단계를 상세히 설명하였다. 삼차원 소자 시뮬레이션을 통해, 제안된 소자의 주요 특징과 특성을 기존 FinFET 및 벌크 FinFET 소자와 비교하였다. 제안된 삼차원 선택적 산화 방식의 핀 채널 MOSFET는 기존의 소자들과 비교하여 더 큰 구동 전류, 더 높은 선형 트랜스컨덕턴스, 더 낮은 직렬 저항을 가지며, 거의 유사한 수준의 소형화 특성을 보이는 것을 확인하였다.

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

키워드

과제정보

This study was supported by the Research Program funded by the SeoulTech(Seoul National University of Science and Technology).

참고문헌

  1. P. Cadareanu, J. Romero-Gonzalez & P. E. Gaillardon. (2021). Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors, IEEE Journal of the Electron Devices Society, 9, 400-408. DOI : 10.1109/JEDS.2021.3070475
  2. S. Nanda & R. S. Dhar. (2021). Implementation and Characterization of 14 nm Trigate HOI n-FinFET using Strained Silicon channel with reduced area on chip, 6th International Conference for Convergence in Technology, 1-4. DOI : 10.1109/I2CT51068.2021.9417877
  3. A. Kumar, P. S. T. N. Srinivas & P. K. Tiwari. (2019). An Insight Into Self-Heating Effects and Its Implications on Hot Carrier Degradation for Silicon-Nanotube-Based Double Gate-All-Around (DGAA) MOSFETs, IEEE J. Electron Dev. Society, 7, 1100-1108. DOI : 10.1109/JEDS.2019.2947604
  4. Y. K. Choi et al. (2001). Sub-20nm CMOS FinFET Technologies, Int. Electron Dev. Meeting, 421-424. DOI : 10.1109/IEDM.2001.979526
  5. C. T. Chuang, P. F. Lu & C. J. Anderson. (1998). SOI for Digital CMOS VLSI: Design Considerations and Advances, Proc. IEEE, 86(4), 689-720. DOI : 10.1109/5.663545
  6. A. Gupta, R. A. Vega, T. B. Hook & A. Dixit. (2020). Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating. IEEE Trans. Electron Dev., 67(5), 2208-2212. DOI : 10.1109/TED.2020.2977734
  7. T. S. Park, H. J. Cho, J. D. Choe, D. Park, E. Yoon & J. H. Lee. (2004). Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions, Jpn. J. Appl. Phys., 43(4B), 2180-2184. DOI : 10.1143/JJAP.43.2180
  8. K. Asano, Y. K. Choi, T. J. King & C. Hu. (2001). Patterning Sub-30-nm MOSFET Gate with I-Line Lithography, IEEE Trans. Electron Dev., 48(5), 1004-1006. DOI : 10.1109/16.918251
  9. Y. K. Choi, T. J. King & C. Hu. (2002). A Spacer Patterning Technology for Nanoscale CMOS, IEEE Trans. Electron Dev., 49(3), 436-441. DOI : 10.1109/16.987114
  10. J. Kedzierski, P. Xuan, E. Anderson, J. Bokor, T. J. King & C. Hu. (2000). Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime, Int. Electron Dev. Meeting, 57-61. DOI : 10.1109/IEDM.2000.904258
  11. Y. K. Choi, D. Ha, T. J. King & C. Hu. (2001). Nanoscale Ultrathin Body PMOSFETs With Raised Selective Germanium Source/Drain, IEEE Electron Dev. Lett., 22(9), 447-448. DOI : 10.1109/55.944335
  12. C. H. Park, M. H. Oh, H. S. Kang & H. K. Kang. (2004). A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications, ETRI Journal, 26(6), 575-582. DOI : 10.4218/etrij.04.0104.0074
  13. O. Faynot & B. Giffard. (1994). High Performance Ultrathin SOI MOSFET's Obtained by Localized Oxidation, IEEE Electron Dev. Lett., 15(5), 175-177. DOI : 10.1109/55.291595
  14. M. Chan, F. Assaderaghi, S. A. Parke, C. Hu & P. K. Ko. (1994). Recessed-Channel Structure for Fabricating Ultrathin SOI MOSFET with Low Series Resistance, IEEE Electron Dev. Lett., 15(1), 22-24. DOI : 10.1109/55.289474
  15. Y. K. Cho, T. Roh & J. Kim. (2005). SoxFET: Three-Dimensional Selective Oxidation Channel MOSFET, Int. Microprocesses and Nanotechnology Conference, 266-267. DOI : 10.1109/IMNC.2005.203840
  16. Y. Taur & T. H. Ning. (1998). CMOS DEVICE DESIGN: Fundamentals of Modern VLSI Devices : Cambridge Univ. Press. DOI : 10.1017/CBO9781139195065
  17. A. M. Waite et. al. (2005). Raised source/ drains for 50 nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy, Solid-State Electronics, 49, 529-534. DOI : 10.1016/j.sse.2005.01.019
  18. H. J. Huang, K. M. Chen, C. Y. Chang, L. P. Chen, G. W. Huang & T. Y. Huang (2000). Reduction of Source/Drain Series Resistance and Its Impact on Device Performance for PMOS Transistors with Raised Si1-xGex Source/Drain, IEEE Electron Dev. Lett., 21(9), 448-450. DOI : 10.1109/55.863107