Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Study on the Circuit Design Methodology and Performance Evaluation for Hybrid Gate Driver

하이브리드 게이트 드라이버를 위한 회로 디자인 방법과 성능 평가에 관한 연구

  • Cho, Geunho (Dept. of Electronics Engineering, Seokyeong University)
  • Received : 2021.06.04
  • Accepted : 2021.06.24
  • Published : 2021.06.30
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Abstract

As Head-Mounted Displays(HMDs), which are mainly used to maximize realism in games and videos, have experienced increased demand and expanded scope of use in education and training, there is growing interest in methods to enhance the performance of conventional HMDs. In this study, a methodology to utilize Carbon NanoTubes(CNTs) to improve the performance of gate drivers that send control signals to each pixel circuit of the HMD is discussed. This paper proposes a new circuit design method that replaces the transistors constituting the buffer part of the conventional gate driver with transistors incorporating CNTs and compare the performance of the suggested gate drive with that of a gate driver comprising only conventional transistors via simulations. According to the simulation results, by including CNTs in the gate driver, the output voltage can be increased by approximately 0.3V compared to the conventional gate driver high voltage(1.1V) at a speed of 12.5 GHz and the gate width also can be reduced by up to 20 times.

과거 주로 게임과 동영상 재생에 있어 리얼함을 극대화하기 위해 사용되었던 HMD(Head Mount Display)의 수요가 증가하고, 그 활용 범위가 교육과 훈련 등으로 확대되면서, 기존 HMD의 성능을 향상시킬 수 있는 방안에 대한 관심이 높아지고 있다. 본 논문에서는 HMD의 각 화소 회로에 제어 신호를 보내는 gate driver의 성능을 향상시키기 위해 CNT를 포함한 트랜지스터를 활용하는 방법에 대해 논하고자 한다. 기존 gate driver의 버퍼부를 구성하는 트랜지스터를 CNT를 포함한 트랜지스터로 교체하는 회로 설계 방법을 제안하고, 그 성능을 회로 시뮬레이션을 통해 기존 트랜지스터로만 구성된 gate driver의 성능과 비교해 보고자 한다. 시뮬레이션 결과, gate driver에 CNT를 포함할 경우 12.5 GHz의 속도로 기존 gate driver 대비 약 0.3V 증가된 출력 전압(1.1V)을 얻을 수 있었으며, 최대 20배의 gate width를 줄일 수 있었다.

Keywords

Acknowledgement

This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (MSIT) (No.2018R1C1B5086081) The EDA tool was supported by the IC Design Education Center(IDEC), Korea

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