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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Function-level module sharing techniques in high-level synthesis

  • Nishikawa, Hiroki (Graduate School of Science and Engineering, Ritsumeikan University) ;
  • Shirane, Kenta (Graduate School of Science and Engineering, Ritsumeikan University) ;
  • Nozaki, Ryohei (Graduate School of Science and Engineering, Ritsumeikan University) ;
  • Taniguchi, Ittetsu (Graduate School of Information Science and Technology, Osaka University) ;
  • Tomiyama, Hiroyuki (Graduate School of Science and Engineering, Ritsumeikan University)
  • Received : 2020.03.21
  • Accepted : 2020.07.02
  • Published : 2020.08.18
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Abstract

High-level synthesis (HLS), which automatically synthesizes a register-transfer level (RTL) circuit from a behavioral description written in a high-level programming language such as C/C++, is becoming a more popular technique for improving design productivity. In general, HLS tools often generate a circuit with a larger area than those of hand-designed ones. One reason for this issue is that HLS tools often generate multiple instances of the same module from a function. To eliminate such a redundancy in circuit area in HLS, HLS tools are capable of sharing modules. Function-level module sharing at a behavioral description written in a high-level programming language may promote function reuse to increase effectiveness and reduce circuit area. In this paper, we present two HLS techniques for module sharing at the function level.

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References

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