Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
권호 표지

A Concurrent Testing of DRAMs Utilizing On-Chip Networks

온칩네트워크를 활용한 DRAM 동시 테스트 기법

  • Lee, Changjin (Hoseo University, School of Electronics and Display Engineering) ;
  • Nam, Jonghyun (Hoseo University, School of Electronics and Display Engineering) ;
  • Ahn, Jin-Ho (Hoseo University, School of Electronics and Display Engineering)
  • 이창진 (호서대학교 전자디스플레이공학부) ;
  • 남종현 (호서대학교 전자디스플레이공학부) ;
  • 안진호 (호서대학교 전자디스플레이공학부)
  • Received : 2020.06.20
  • Accepted : 2020.06.24
  • Published : 2020.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

Keywords

References

  1. www.mk.co.kr/news/business/view/2020/03/308030
  2. V. C. Khoo, "Cost of Test Case for Multi-site Testing in Semiconductor Industry with Firm Theory", Int. Journal of Business and Management Invention," Vol. 3, No. 4, pp.14-27, April 2014.
  3. B. Li, B. Zhang, and V. D. Agrawal, "Adopting Multi- Valued Logic for Reduced Pin-Count Testing", Proc. of Latin American Test Symposium(LATS), pp. 1-6, 2015.
  4. D. Han, Y. Lee, and S. Kang, "A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture", ETRI Journal, Vol. 36, No. 2, pp. 293-300, 2014. https://doi.org/10.4218/etrij.14.0113.0469
  5. S. Seo, H. Lim, S. Kang, and S. Kang, "Off-Chip Test Architecture for Improving Multi-Site Testing Efficiency using Tri-State Decoder and 3V-Level Encoder", Proc. of Intl. Symp. on Quality Elec. Design(ISQED), 2017.
  6. C.-C. Yang, J.-F. Li, Y.-C. Yu, K.-T. Wu, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, and Y.-F. Chou, "A hybrid built-in self-test scheme for DRAMs", Proc. of VLSIDAT, April 2015.
  7. H.-H. Liu, B.-Y. Lin, C.-W. Wu, W.-T. Chiang, L. Mincent, H.-C. Lin, C.-N. Peng, and M.-J. Wang, "A Built-Off Self-Repair Scheme for Channel-Based 3D Memories" , IEEE Trans. On Computers, Vol. 66, No. 8, pp. 1293-1301, Feb. 2017. https://doi.org/10.1109/TC.2017.2667645
  8. W. Kang, C. Lee, H. Lim, and S. Kang, "Optimized Built-In Self-Repair for Multiple Memories", IEEE Trans. On VLSI, Vol. 24, No. 6, pp. 2174-2183, Dec. 2015.
  9. TechWing Technical Report, Korea IR Service, 2020. 1
  10. C. Hong and J. Ahn, "Improving Parallel Testing Efficiency of Memory Chips using NOC Interconnect", Trans. of KIEE, Vol. 68, No. 2, pp. 364-369, 2019. https://doi.org/10.5370/KIEE.2019.68.2.364
  11. C. Hong and J. Ahn, "The Method of Parallel Test Efficiency Improvement using Multi-Clock Mode", Journal of the Semiconductor & Display Technology, Vol. 18, No. 3. Sep. 2019.
  12. T. Bjerregaard and S. Mahadevan, "A survey of research and practices of Network-on-chip", ACM Computing Surveys, Vol. 38, No. 1, pp. 1-51, 2006. https://doi.org/10.1145/1132952.1132953
  13. W. Zhang, L. Hou, J. Wang, S. Geng, and W. Wu, "Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip", Proc. of WRI GCIS, 2009.
  14. M. A. Kochte and H.-J. Wunderlich, "Self-Test and Diagnosis for Self-Aware Systems", IEEE Design & Test, Vol. 35, No. 5, Oct. 2018.
  15. M. Hosseinabady, A. Banaiyan, M.N. Bojnordi, and Z. Navabi, "A concurrent testing method for NoC switches", Proc. of DATE, March 2006.
  16. Y. Zhang, K. Chakrabarty, H. Li, and J. Jiang, "Software-based online self-testing of network-on-chip using bounded model checking", Proc. of ITC, Oct. 2017.
  17. J. Wang, M. Ebrahimi, L. Huang, X. Xie, Q.Li, G. Li, and A. Jantsch, "Efficient Design-for-Test Approach for Networks-on-Chip", IEEE Trans. On Computers, Vol. 68, No. 2, pp. 198-213, Aug. 2018. https://doi.org/10.1109/tc.2018.2865948
  18. T. Han, I. Choi, H. Oh, and S. Kang, "Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores", IEEE Trans. On ICCAD, Vol. 35, No. 7, pp. 1219-1223, July 2016.