Fig. 1 Start and stop signals in time-to-digital converter
Fig. 2 Time-to-digital converter (a) conventional countertype time-to-digital converter (b) proposed counter-type time-to-digital converter
Fig. 4 The proposed time-to-digital converter
Fig. 3 Input and output signals in conventional time-todigital converter
Fig. 5 Input and output signals of the proposed time-to-digital converter (a)
Fig. 6 Dual edge triggered T flip flop circuit
Fig. 7 Clock, input TIN and output Q signals of the dual edge triggered T flip flop (a) clock signal (b) TIN signal (c) Q signal
Fig. 8 Input and output signals of time-to-digital converter (a) start signal (b) stop sugnal (c) counter outputs when SEFF(single-edge flip flops) and DEFF(dual-edge flip flops) are used.
References
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