그림 1. 제안된 회로의 전체 구조 Fig. 1 Overall structure of the proposed circuit
그림 2. CML PD와 CMOS PD 소모전력 Fig. 2 Power consumptions of CML and CMOS PDs
그림 3. 위상 스플리터의 회로도 Fig. 3 Schematic of the phase splitter
그림 4. 위상 스플리터 입출력 신호 Fig. 4 Input/output of the phase splitter
그림 5. VCDL의 회로도 Fig. 5 Schematic of the VCDL
그림 6. Vcont에 따른 VCDL delay의 변화 Fig. 6 Change of VCDL delay according to Vcont
그림 7. 레벨 변환기의 회로도 Fig. 7 Schematic of the level converter
그림 8. 위상 스플리터 시뮬레이션 결과 Fig. 8 Simulation result of the phase splitter
그림 9. 위상 스플리터의 듀티 사이클 특성 Fig. 9 Simulated duty cycle of the phase splitter
그림 10. 제안된 DLL의 (a)동작과 (b)위상 오차 Fig. 10 (a) Operation and (b) phase error of the proposed DLL
그림 11. 제안된 DLL의 지터 Fig. 11 Jitter of Proposed DLL
표 1. 인버터 구성 비율 Table. 1 Size ratio of Inverter
표 2. 제안된 DLL 특성 요약 Table. 2 Summary of the proposed DLL (at 1GHz, nn, 1.2V, 27℃)
References
- S. Yeo, J. Kim, T. Cho, S. Cho, and S. Kim, "Design of Low Power Current Memory Circuit based on Voltage Scaling," J. of the Korea Institute of Electronic Communication Science, vol. 11, no. 2, 2016, pp. 159-164. https://doi.org/10.13067/JKIECS.2016.11.2.159
- H. Moon, H. Kal, and W. Lee, "Study on Structure and Principle of Linear Block Error Correction Code," J. of the Korea institute of Electronic Communication Science, vol. 13, no. 4, 2018, pp. 721-728. https://doi.org/10.13067/JKIECS.2018.13.4.721
- S. Yeo, T. Cho, Y. Shin, and S. Kim, "Design of OTA Circuit for Current-mode FIR Filter," J. of the Korea Institute of Electronic Communication Science, vol. 11, no. 7, 2016, pp. 659-664. https://doi.org/10.13067/JKIECS.2016.11.7.659
- H. Park, J. Kwon, T. Hwang, and D. Kim, "A Development of Fusion Processor Architecture for Efficient Main Memory Access in CPU-GPU Environment," J. of the Korea Institute of Electronic Communication Science, vol. 11, no. 2, 2016, pp. 151-158. https://doi.org/10.13067/JKIECS.2016.11.2.151
- B. Kim, J. Lee, T. Hwang, and D. Kim, "Design of Lightweight Artificial Intelligence System for Multimodal Signal Processing," J. of the Korea Institute of Electronic Communication Science, vol. 13, no. 5, 2018, pp. 1037-1042. https://doi.org/10.13067/JKIECS.2018.13.5.1037
- K. Kim and J. Chong, "Mesochronous Clock Based Synchronizer Design for NoC," J. of the Korea Institute of Electronic Communication Science, vol. 10, no. 10, 2015, pp. 1123-1130. https://doi.org/10.13067/JKIECS.2015.10.10.1123
- Y. Moon, J. Choi, K. Lee, D. Jeong, and M. Kim, "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter," IEEE J. of Solid-State Circuits, vol. 35, no. 3, Mar. 2000, pp. 377-384. https://doi.org/10.1109/4.826820
- D. Rennie and M. Sachdev, "Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuit," IEEE Int. Symp. on Quality Electronics Design, San Jose, USA, 2007.
- J. Maneatis, "Low Jitter Process Independent DLL based on Self-Biased Techniques," IEEE J. of Solid-State Circuits, vol. 31, no. 11, Nov. 1996, pp. 1723-1732. https://doi.org/10.1109/JSSC.1996.542317
- D. Kim, "Complementary clock generator and method for generating complementary clocks," United States Patent, no. 5867043, Feb. 2, 1999.