Fig. 1. Normalized impulse response of a 30 inch FR-4 backplane channel[1]
Fig. 2. Channel-Backplane
Fig. 3. Performance comparison of NRZ, DB, and PR4 signaling over Tyco channel #1 with data rate of 10.3Gb/s with the worst case NEXT[2]
Fig. 4. Typical TX pre-emphasis schemes
Fig. 5. Different Equalization Schemes: (a) LE; (b) DFE; (c) LE+DFE.[2]
Fig. 6. 5-tap transversal equalizer structures
Fig. 7. 3rdorder delay Cell
Fig. 8. Summing Circuit and I/V Converter
Fig. 9. Classifications of Receiver Equalizers
Fig. 10. Block Diagram of conventional Continuous-time adaptive Cable equalizer[15]
Fig. 11. Power vs Frequency
Fig. 12. input 1Gbps (a) magnitude response vs Frequency (b) eye diagram of after equalization
Fig. 13. Power spectrum vs Frequency
Fig. 14. VGA gain A vs Time (us)
Fig. 15. Transient simulation (a) up part TX+Channel (b) down TX+Channel+Equalizer filter
Fig. 16. Block Diagram of Continuous-time adaptive Cable equalizer with Clock
Fig. 17. Power spectrum vs Frequency input and input+channel
Fig. 18. VGA gain A vs Time (us)
Fig. 19. Transient simulation (a) up part TX+ Channel (b) down TX+Channel+Equalizer filter
Fig. 20. input 1Gbps (a) Eye diagram of Before equalization (b) eye diagram of after equalization
Table 1. System Environment
Table 2. Value A that depends on type of power detecting filter and their frequency
References
- Charles E. Berndt, Tad A. Kwasniewski: A Review of Common Receive-End Adaptive and Algorithms for a High-Speed Serial Backplane. IWSOC 2005: 149-153
- Cathy Ye Liu, LSI Logic "Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps)" Designcon 2007, SantaClara,CA
- A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M. A. Horowitz, "Common-mode Backchannel Signaling System for Differential High-speed Links," IEEE Symposium on VLSI Circuits, June 2004.
- R. Payne et al., "A 6.25-Gb/s binary transceiver in 0.13-_m CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Circuits, vol. 40, no. 12, pp. 2646-2657, Dec.2005. https://doi.org/10.1109/JSSC.2005.856583
- T. Beukema et al., "A 6.4-Gb/s CMOS serDes core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005. https://doi.org/10.1109/JSSC.2005.856584
- K. Krishna, D. A. Yokoyama-Martin, S. Wolfer, C. Jones, M. Loikkanen, J. Parker, R. Segelken, J. L. Sonntag, J. Stonick, S. Titus, and D. Weinlader, "A multigigabit backplane transceiver core in 0.13 _m CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Solid-State Circuits, pp. 2658-2666, Dec. 2005.
- Ravi Kollipara et.al. "Impact of Manufacturing Variations on Backplane System Performance" DesignCon 2005, SantaClara,CA
- Jared Zerbe et. al. "Comparison of adaptive and non-adaptive equalization methods in high-performance backplanes" DesignCon 2005, SantaClara,CA
- A. Shoval, O. Shoaei, K. Lee, and R. Leonwich, CMOS mixed-signal 100 Mb/s receive architecture for fast ethernet," in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp. 253-256.
- M. Altmann, J. M. Caia, R. Morle, M. Dunsmore, Y. Xie, and N. Kocaman, "A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax & fiber," in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 127-130.
- T. Ellermeyer, U. Langmann, B. Wedding, and W. Pohlmann, "A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver," in Proc. IEEE Int. Solid-State Circuits Conf., 2000, pp. 50-51.
- X.F. Lin and J. Liu, "A Digital Power Spectrum Estimation Method for the Adaptation of High-speed Equalizer," IEEE Transactions on Circuits and Systems I, vol. 51, pp. 2436-2443, Dec. 2004. https://doi.org/10.1109/TCSI.2004.838250
- D. Hernandez-Garduno, Jose Silva-Martinez, "A CMOS 1Gb/s 5-Tap Transversal Equalizer based on Inductor-Less Third-Order Delay Cells", to be presented in ISSCC Feb. 2007.
- S. Gondi, "A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications," IEEE ISSCC Dig. Tech. Papers, Feb.2004, pp. 328-329.
- J.-S. Choi et al., "A 0.18um CMOS 3.5Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method," IEEE J. Solid-State Circuits, pp. 419-425, March, 2004.