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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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CMOS true-time delay IC for wideband phased-array antenna

  • Kim, Jinhyun (Department of Electronic Engineering, Kwangwoon University) ;
  • Park, Jeongsoo (Department of Electronic Engineering, Kwangwoon University) ;
  • Kim, Jeong-Geun (Department of Electronic Engineering, Kwangwoon University)
  • Received : 2018.03.02
  • Accepted : 2018.05.03
  • Published : 2018.12.06
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Abstract

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

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References

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