• Title/Summary/Keyword: true-time delay

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WDM Optical True Time-Delay for X-Band Phased Array Antennas (X-밴드 위상 배열 안테나를 위한 WDM 광 실시간 지연선로)

  • Jung, Byung-Min;Shin, Jong-Dug;Kim, Boo-Gyoun
    • Korean Journal of Optics and Photonics
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    • v.18 no.2
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    • pp.162-166
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    • 2007
  • In this paper, we propose a WDM optical true time-delay (OTTD) beam former for phased way antenna (PAA) systems. It is composed of a delay lines matrix and a multiwavelength source with discrete DFB laser diodes. The building block of a delay lines matrix is a $2\times2$ optical MEMS switch with proper fiber-optic delay line connected between cross ports. A $4\times3$ matrix using four DFB lasers has been fabricated with unit time-delay difference of 12 ps. Maximum time-delay error was measured to be -1.74 ps and +1.14 ps at a radiation angle of $46.05^{\circ}$, corresponding to error range of $-2.87^{\circ}\sim+1.88^{\circ}$. By measuring time-delays at six different RF frequencies from 5- to 10-GHz, we verified the true time-delay characteristic of our OTTD.

Optical True Time-Delay for Planar Phased Array Antennas Composed of a FBG Prism and a Fiber Delay Lines Matrix (FBG 프리즘과 광섬유 지연선로 행렬을 이용한 평면 위상 배열 안테나용 광 실시간 지연선로)

  • Jung, Byung-Min;Shin, Jong-Dug;Kim, Boo-Gyoun
    • Korean Journal of Optics and Photonics
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    • v.17 no.1
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    • pp.7-17
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    • 2006
  • In this paper, we proposed an optical true time-delay (TTD) for planar phased array antennas (PAAs), which is composed of a wavelength-dependent optical true time delay (WDOTTD) followed by a wavelength-independent optical true time delay (WIOTTD). The WDOTTD is a fiber Bragg gratings (FBGs) Prism and the WDOTTD is a fiber delay-lines matrix of which each component consists of a certain length of fiber connected to cross-ports of a 2${\times}$2 MEMS switch. A 10-GHz 2-bit${\times}$4-bit two-dimensional optical TTD has been fabricated by cascading a WDOTTD with a maximum time delay of 810 ps to a WIOTTD of $\pm$50 ps. Time delay and insertion loss for each radiation angle have been measured. Time delay error for the WIOTTD has been measured to be less than $\pm$1 ps. We have also designed a two-dimensional 10-GHz PAA composed of 8${\times}$8 microstrip patch antenna elements driven by the proposed TTD. The radiation patterns of this PAA have been obtained by simulation and analyzed.

Photonic True-Time Delay for Phased-Array Antenna System using Dispersion Compensating Module and a Multiwavelength Fiber Laser

  • Jeon, Hyun-Bin;Lee, Hojoon
    • Journal of the Optical Society of Korea
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    • v.18 no.4
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    • pp.406-413
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    • 2014
  • An optical true-time delay beam-forming system using a tunable dispersion compensating module (DCM) for dense-wavelength division modulation (DWDM) and a multiwavelength fiber ring laser for a phased array antenna is proposed. The multiwavelength fiber ring laser has one output that includes four wavelengths; and four outputs that include only single-wavelength. The advantage of such a multiwavelength fiber ring laser is that it minimizes the number of devices in the phased array antenna system. The time delays according to wavelengths, which are assigned for each antenna element, are obtained from the tunable DCM. The tunable DCM based on a temperature adjustable Fabry-Perot etalon is used. As an experimental result, a DCM could be used to obtain the change of the beam angle by adjusting the dispersion value of the DCM at the fixed lasing wavelengths of the fiber ring laser in the proposed optical true-time delay.

A 5-20 GHz 5-Bit True Time Delay Circuit in 0.18 ㎛ CMOS Technology

  • Choi, Jae Young;Cho, Moon-Kyu;Baek, Donghyun;Kim, Jeong-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.3
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    • pp.193-197
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    • 2013
  • This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

A Study on Configuration of True Time Delay Phase Shifter for Wideband Beam Steering Phased Array Antenna (광대역 빔 조향을 위한 위상 배열 안테나의 실시간 지연 위상 천이기 구성에 관한 연구)

  • Jung, Jinwoo;Ryu, Jiho;Park, Jaedon;Seo, Jongwoo
    • Journal of the Korea Institute of Military Science and Technology
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    • v.20 no.3
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    • pp.413-420
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    • 2017
  • We investigate the performance of a true time delay(TTD) phase shifter to reduce the beam squint caused by frequency changes of a phased array antenna in wideband communication systems. To design a high gain phased array antenna, we need a long TTD, which causes high RF loss, low resolution and large dimension of TTD phase shifters. To overcome the problems, we propose a schematic of dual TTD phase shifters, which consists of short time delay(STD) in radio frequency(RF) part and long time delay(LTD) in intermediate frequency(IF) part. Our analysis results show that the proposed scheme reduces the required bits and delay time in RF band of the TTD compared to the conventional single TTD scheme.

CMOS true-time delay IC for wideband phased-array antenna

  • Kim, Jinhyun;Park, Jeongsoo;Kim, Jeong-Geun
    • ETRI Journal
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    • v.40 no.6
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    • pp.693-698
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    • 2018
  • This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

Design of a 6~18 GHz 8-Bit True Time Delay Using 0.18-㎛ CMOS (0.18-㎛ CMOS 공정을 이용한 6~18 GHz 8-비트 실시간 지연 회로 설계)

  • Lee, Sanghoon;Na, Yunsik;Lee, Sungho;Lee, Sung Chul;Seo, Munkyo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.11
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    • pp.924-927
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    • 2017
  • This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

A Study of 0.5-bit Resolution for True-Time Delay of Phased-Array Antenna System

  • Cha, Junwoo;Park, Youngcheol
    • International journal of advanced smart convergence
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    • v.11 no.4
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    • pp.96-103
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    • 2022
  • This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm2. In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

Voltage-Controlled Photonic RF True-Time Delay Using a Tapered Chirped Fiber Bragg Grating (테이퍼 구조를 갖는 광섬유 브래그 격자를 이용한 전압에 의하여 제어 가능한 광학적 실시간 지연 소자)

  • Chae, Ho-Dong;Lee, Sang-Shin
    • Korean Journal of Optics and Photonics
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    • v.16 no.2
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    • pp.133-137
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    • 2005
  • A photonic RF true-time delay using a tapered chirped fiber Bragg grating coated with a heating electrode has been proposed and fabricated. For an RF signal carried over an optical signal, the time delay has been achieved by controlling the voltage applied to the electrode and thus adjusting its reflection positions from the fiber grating through the thermooptic effect. It features continuous voltage-controlled operation, requiring no mechanical perturbation and no moving parts. The measured time delay was about 120 ps with the electrical power consumption of $250{\cal}mW$.

Adaptive Time Delay Compensation Process in Networked Control System

  • Kim, Yong-Gil;Moon, Kyung-Il
    • International journal of advanced smart convergence
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    • v.5 no.1
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    • pp.34-46
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    • 2016
  • Networked Control System (NCS) has evolved in the past decade through the advances in communication technology. The problems involved in NCS are broadly classified into two categories namely network issues due to network and control performance due to system network. The network problems are related to bandwidth allocation, scheduling and network security, and the control problems deal with stability analysis and delay compensation. Various delays with variable length occur due to sharing a common network medium. Though most delays are very less and mostly neglected, the network induced delay is significant. It occurs when sensors, actuators, and controllers exchange data packet across the communication network. Networked induced delay arises from sensor to controller and controller to actuator. This paper presents an adaptive delay compensation process for efficient control. Though Smith predictor has been commonly used as dead time compensators, it is not adaptive to match with the stochastic behavior of network characteristics. Time delay adaptive compensation gives an effective control to solve dead time, and creates a virtual environment using the plant model and computed delay which is used to compensate the effect of delay. This approach is simulated using TrueTime simulator that is a Matlab Simulink based simulator facilitates co-simulation of controller task execution in real-time kernels, network transmissions and continuous plant dynamics for NCS. The simulation result is analyzed, and it is confirmed that this control provides good performance.