Electronics and Telecommunications Trends (전자통신동향분석)

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Next-Generation Neuromorphic Hardware Technology

차세대 뉴로모픽 하드웨어 기술 동향

  • Published : 2018.12.01
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Abstract

A neuromorphic hardware that mimics biological perceptions and has a path toward human-level artificial intelligence (AI) was developed. In contrast with software-based AI using a conventional Von Neumann computer architecture, neuromorphic hardware-based AI has a power-efficient operation with simultaneous memorization and calculation, which is the operation method of the human brain. For an ideal neuromorphic device similar to the human brain, many technical huddles should be overcome; for example, new materials and structures for the synapses and neurons, an ultra-high density integration process, and neuromorphic modeling should be developed, and a better biological understanding of learning, memory, and cognition of the brain should be achieved. In this paper, studies attempting to overcome the limitations of next-generation neuromorphic hardware technologies are reviewed.

Keywords

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(그림 1) 뉴로모픽 공학 연구 개념도

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(그림 2) Integrate-and-fire 뉴런 모델 블록 다이어그램과 수학적 모델

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(그림 3) 강유전체 분극 반전과 금속 이온 이동을 동시에 이용하는 멤리스터 소자의 동작 원리와 측정 결과

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(그림 4) 뉴로모픽 모델링 및 인식 성능 평가 기술

<표 1> CMOS 기반 뉴로로픽 시스템과 인체 뇌와의 성능 비교

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References

  1. I.K. Schuller et al., "Neuromorphic Computing: From Materials to Systems Architecture," Report of a Roundtable Convened to Consider Neuromorphic Computing Basic Research Needs, 2015, pp. 1-37.
  2. G. Indiveri et al., "Neuromorphic silicon neuron circuits," Frontiers Neurosci,. vol. 5, May 2011, pp. 1-23.
  3. C. Mead, "Neuromorphic Electronic Systems," Proc. IEEE, vol. 78, no. 10, Oct. 1990, pp. 1629-1636. https://doi.org/10.1109/5.58356
  4. J. Park et al., "Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems," IEEE Trans. Neural Netw. Learning Syst., vol. 28, no. 10, Oct. 2017, pp. 2408-2422. https://doi.org/10.1109/TNNLS.2016.2572164
  5. L. Lapicque, "Recherches Quantitatives sur L'excitation E´lectrique des Nerfs Traite'e Comme une Polarization," J. Physiol. Pathol. Gen., vol. 9, 1907, pp. 620-635.
  6. M.D. Pickett et al., "A Scalable Neuristor Built with Mott Memristors," Nat. Mater., vol. 12, Dec. 2013, pp. 144-147.
  7. J. Lin et al., "Low-Voltage Artificial Neuron Using Feedback Engineered Insulator-to-Metal-Transition Devices," in Int. Electon. Dev. Meeting, San Francisco, CA, USA, Dec. 3-7, 2016, p. 34.5.1-34.5.4.
  8. P. Stoliar et al., "A Leaky-Interate-and-Fire Neuron Analog Realized with a Mott Insulator," Adv. Funct. Mater., vol. 27, no. 11, Mar. 2017, pp. 1-7.
  9. T. Tuma et al., "Strochastic Phase-Change Neurons," Nat. Nanotech., vol. 11, 2016, pp. 693-670. https://doi.org/10.1038/nnano.2016.70
  10. X. Zhang et al., "An Artificial Neuron Based on a Threshold Switching Memristor," IEEE Electron Dev. Lett., vol. 39, no. 2, Feb. 2018, pp. 308-311. https://doi.org/10.1109/LED.2017.2782752
  11. A. Jaiswal et al., "Proposal for a Leaky-Integrate-Fire Spiking Neuron Based on Magnetoelectric Switching of Ferromagnets," IEEE Trans. Electr. Dev., vol. 64, no. 4, Apr. 2017, pp. 1818-1824. https://doi.org/10.1109/TED.2017.2671353
  12. Z. Wang et al., "Fully Memristive Neural Networks for Pattern Classification with Unsupervised Learning," Nat. Electron., vol. 11, 2018, pp. 137-145.
  13. T. Ohno et al., "Short-Term Plasticity And Long-Term Potentiation Mimicked In Single Inorganic Synapses," Nature Mat., vol. 10, 2011, pp. 591-595. https://doi.org/10.1038/nmat3054
  14. Z. Wang et al., "Memristors with Diusive Dynamics as Synaptic Emulators for Neuromorphic Computing," Nature Mat., vol. 16, 2017, pp. 101-110. https://doi.org/10.1038/nmat4756
  15. L. Hu, "Ultrasensitive Memristive Synapses Based on Lightly Oxidized Sulfide Films," Adv. Mater., vol. 29, no. 24, 2017, pp. 1-11.
  16. S. Choi et al., "Experimental Demonstration of Feature Extraction and Dimensionality Reduction Using Memristor Networks," Nano Lett., vol. 17, no. 5, 2017, pp. 3113-3118. https://doi.org/10.1021/acs.nanolett.7b00552
  17. T. Chang et al., "Short-Term Memory to Long-Term Memory Transition in a Nanoscale Memristor," ACS Nano, vol. 5, no. 9, 2011, pp. 7669-7676. https://doi.org/10.1021/nn202983n
  18. Z.H. Tan et al., "Synaptic Metaplasticity Realized in Oxide Memristive Devices," Adv. Mater., vol. 28, no. 2, Jan. 2016, pp. 377-384. https://doi.org/10.1002/adma.201503575
  19. D. Kuzum et al., "Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing," Nano Lett., vol. 12, no. 5, 2012, pp. 2179-2186. https://doi.org/10.1021/nl201040y
  20. C.D. Wright et al., "Arithmetic and Biologically-Inspired Computing Using Phase-Change Materials," Adv. Mater., vol. 23, no. 30, Aug. 2011, pp. 3408-3413. https://doi.org/10.1002/adma.201101060
  21. X. Wang et al., "Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion," IEEE Electr. Dev. Lett., vol. 30, no. 3, Mar. 2009, pp. 294-297. https://doi.org/10.1109/LED.2008.2012270
  22. G. Srinivasan et al., "Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning," Sci. Rep., vol. 6, 2016, Article no. 29545.
  23. S. Kim et al., "Pattern Recognition Using Carbon Nanotube Synaptic Transistors with an Adjustable Weight Update Protocol, " ACS Nano, vol. 11, no. 3, 2017, pp. 2814-2822. https://doi.org/10.1021/acsnano.6b07894
  24. Y. Burgt et al., "A Non-Volatile Organic Electrochemical Device as a Low-Voltage Artificial Synapse for Neuromorphic Computing," Nature Mat., vol. 16, 2017, pp. 414-419. https://doi.org/10.1038/nmat4856
  25. C.S. Yang et al., "A Synaptic Transistor based on Quasi-2D Molybdenum Oxide," Adv. Mater., vol. 29, no. 27, July 2017, Article no. 1700906.
  26. J. Shi et al., "A correlated nickelate synaptic transistor," Nature Commun., vol. 4, 2013, Article no. 2676.
  27. Y.M. Kim et al., "Short-Term and Long-Term Memory Operations of Synapse Thin-Film Transistors using an In-Ga-Zn-O Active Channel and a Poly(4-vinylphenol)-Sodium ${\beta}$-Alumina Electrolytic Gate Insulator," RSC Adv., vol. 6, 2017, pp. 52913-52919.
  28. F. Shao at al., "Oxide-Based Synaptic Transistors Gated by Sol-Gel Silica Electrolytes," ACS Appl. Mater. Interfaces, vol. 8, 2016, pp. 3050-3055. https://doi.org/10.1021/acsami.5b10195
  29. C. Wan et al., "Classical Conditioning Mimicked in Junctionless IZO Electric-Double-Layer Thin-Film Transistors," IEEE Electr. Dev. Lett., vol. 35, no. 3, Mar. 2014, pp. 414-416. https://doi.org/10.1109/LED.2014.2299796
  30. S.M. Yoon et al., "An Electrically Modifiable Synapse Array Composed of Metal-Ferroelectric-Semiconductor (MFS) FET's using SrBi2Ta2O9 Thin Films," IEEE Electron. Dev. Lett., vol. 20, no. 5, May 1999, pp. 229-231. https://doi.org/10.1109/55.761023
  31. S.M. Yoon et al., "Adpative-Learning Neuron Integrated Circuits Using Metal-Ferroelectric (SrBi2Ta2O9)-Semiconductor (MFS) FET's," IEEE Electron. Dev. Lett., vol. 20, no. 5, May 1999, pp. 526-528. https://doi.org/10.1109/55.791931
  32. S.M. Yoon et al., "Ferroelectric Neuron Integrated Circuits Using SrBi2Ta2O9-Gate FET's and CMOS Schmitt-Trigger Oscillators," IEEE Trans. Electron. Dev., vol. 47, no. 8, Aug. 2000, pp. 1630-1635. https://doi.org/10.1109/16.853041
  33. A. Chanthbouala et al., "A Ferroelectric Memristor," Nature Mater., vol. 11, Sept. 2012, pp. 860-864. https://doi.org/10.1038/nmat3415
  34. S. Boyn et al., "Learning Through Ferroelectric Domain Dynamics in Solid-State Synapses," Nature Commun., vol. 8, Apr. 2017, Article no. 14736.
  35. C. Yoon et al., "Synaptic Plasticity Selectively Activated by Polarization-Dependent Energy-Efficient Ion Migration in an Ultrathin Ferroelectric Tunnel Junction," Nano Lett., vol. 17, no. 3, 2017, pp. 1949-1955. https://doi.org/10.1021/acs.nanolett.6b05308
  36. K. Likharev et al., "CrossNets: High-Performance Neuromorphic Architectures for CMOL Circuits," Annu. NY Acad. Sci., vol. 1006, no. 1, Dec. 2003, pp. 146-163. https://doi.org/10.1196/annals.1292.010
  37. K. Likharev, "CrossNets: Neur Omorphic Hybrid CMOS/Nanoelectronic Networks," Sci. Adv. Mater., vol. 3, no. 3, June 2011, pp. 322-331. https://doi.org/10.1166/sam.2011.1177
  38. D.B. Strukov et al., "CMOL FPGA: a Reconfigurable Architecture for Hybrid Digital Circuits with Two-Terminal Nanodevices," Nanotechnol., vol. 16, no. 6, Apr. 2005, pp. 888. https://doi.org/10.1088/0957-4484/16/6/045
  39. P. Lin et al., "3D Integration of Planar Crossbar Memristive Devices with CMOS Substrate," Nanotechnol., vol. 25, no. 40, 2014, Article no. 405202.
  40. M. Jo et al., "Novel Cross-Point Resistive Switching Memory with Self-Formed Schottky Barrier," Symp. VLSI Technol., Honolulu, HI, USA, June 15-17, 2010, pp. 53-54.
  41. M. Lee et al., "Brain-Inspired Photonic Neuromorphic Devices using Photodynamic Amorphous Oxide Semiconductors and their Persistent Photoconductivity," Adv. Mater., vol. 29, no. 28, July 2017, Article no. 1700951.
  42. S. Qin et al., "A Light-Stimulated Synaptic Device Based on Graphene Hybrid Phototransistor," 2D Mater., vol. 4, no. 3, Aug. 2017, Article no. 035022.
  43. http://www.panasonic.co.jp/corp/news/official.data/data.dir/2013/06/en130610-3/en130610-3.html
  44. Moon et al., "High Density Neuromorphic System with Mo/Pr0.7Ca0.3MnO3 Synapse and NbO2 IMT Oscillator Neuron," IEEE Int. Electr. Dev. Meeting, Washington, DC, USA, Dec. 7-9, 2015, pp. 17.6.1-17.6.4.
  45. G.W. Burr et al., "Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element," IEEE Trans. Electr. Dev., vol. 62, no. 11, Nov. 2015, pp. 3498-3507. https://doi.org/10.1109/TED.2015.2439635
  46. http://caffe.berkeleyvision.org/
  47. https://www.tensorflow.org/
  48. http://deeplearning.net/software/theano/
  49. http://torch.ch/
  50. P. Gysel et al., "Hardware-Oriented Approximation of Convolutional Neural Networks," Int. Conf. Learn. Representations, San Juan, Puerto Rico, May 2-4, 2016, pp. 1-8.
  51. S. Han et al., "Learning Both Weights and Connections for Efficient Neural Network." In Proc. Int. Conf. Neural Inform. Process. Syst., Montreal, Canada, Dec. 7-12, 2015, 2016, pp. 1135-1143.
  52. S. Han et al., "Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding," Proc. Int. Conf. Neural Inform. Process. Syst., Montreal, Canada, Dec. 7-12, 2015, pp. 1-9.
  53. C. Du et al., "Reservoir Computing Using Dynamic Memristors for Temporal Information Processing," Nature Commun., vol. 8, 2017, Article no. 2204.