전기전자학회논문지 (Journal of IKEEE)

  • 제21권1호
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  • Pages.7-12
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  • 2017
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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높은 홀딩 전압을 갖는 세그먼트 레이아웃 기법을 이용한 SCR 기반 ESD 보호회로에 관한 연구

Study on the SCR-based ESD Protection Circuit Using the Segmentation Layout Technique with High Holding Voltage

  • Park, Jun-Geol (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Do, Kyoung-Il (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Chae, Hee-Guk (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Seo, Jeong-Yun (Dept. of Electronics Engineering, DanKook Unversity) ;
  • Koo, Yong-Seo (Dept. of Electronics Engineering, DanKook Unversity)
  • 발행 : 2017.03.31
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 Latch-up 면역과 우수한 면적 효율성을 갖는 고전압용 ESD 보호회로를 제안한다. 제안된 회로는 기존의 SCR에 대하여 플로팅 영역 삽입과 세그먼트 레이아웃 기법을 적용함에 따라 매우 높은 홀딩 전압을 갖는다. 제안된 ESD 보호회로는 세그먼트 레이아웃 기법을 이용하여 높은 면적 효율을 지닌다. 제안된 소자는 일반적인 SCR의 3.39V의 홀딩 전압과 비교하여 21.67V의 높은 홀딩 전압을 가진다. 제안된 소자의 전기적 특성은 Synopsys사의 TCAD를 통해 검증하였으며, 0.18 BCD 공정을 이용한 실제 제작을 통해 증명하였다.

This paper proposed the ESD protection circuit for the high-voltage applications with latch-up immunity and high area efficiency. The proposed circuit has high holding voltage compared to the conventional SCR by inserting the floating regions and applying the segmentation layout. It has the area efficiency is more higher due to the segmentation layout. The proposed circuit has the higher holding voltage of the 21.67V than the 3.39V of the conventional SCR. The electrical characteristics of the proposed circuit was investigated by TCAD simulator, and was proved through the fabrication by using the 0.18 BCD process.

키워드

참고문헌

  1. A. Wang, On-Chip ESD Protection for Integrated Circuits (2nd ed.), Springer, 2002. DOI : 10.1007/b117005
  2. C. Russ, K. Bock, M. Rasras, I. Wolf, G. Groeseneken, and H. Maes, "Non-uniform triggering of gg-nMOSt investigated by combined emission microcopy and transmission line pulsing," Proceedings of Electrical Overstress / Electrostatic Discharge Symposium (EOS/ESD1998), pp. 177-186, 1998. DOI : 10.1109/EOSESD.1998.737037
  3. J. Lee "Analysis of SCR, MVSCR, LVTSCR with I-V Characteristic and Turn-On-Time," j.inst.Korean.electr.electron.eng, vol. 20, no. 3, pp. 295-398, 2016. DOI : 10.7471/ikeee.2016.20.3.295
  4. O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H. Zwol, "ESD protection for high-voltage CMOS technologies," Proceedings of Electrical Overstress / Electrostatic Discharge Symposium (EOS/ESD 2006), pp. 77-86, 2006. DOI : 10.1109/EOSESD.2006.5256797
  5. Z. Liu, J. Liou, and J. Vinson, "Novel silicon controller rectifier (SCR) layout topology for high-voltage electrostatic discharge (ESD) applications," IEEE Electron Device Letter , vol. 29. no. 7, pp. 753-755, 2008. DOI : 10.1109/LED.2008.923711
  6. Z. Liu, J. He, J. Liou, J. Liu, M. Miao, and S. Dong, "Segmented SCR for High Voltage ESD Protection," Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT2012), pp. 1-4 2012. DOI : 10.1109/ICSICT.2012.6467917
  7. J. Barth, K. Verhaege, and L. Henry, "TLP Calibration, Correlation, Standards, and New Techniques," Proceedings of Electrical Overstress / Electrostatic Discharge Symposium (EOS/ESD2000), pp. 85-96, 2000. DOI : 10.1109/EOSESD.2000.890031