JSTS:Journal of Semiconductor Technology and Science

  • 제17권2호
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  • Pages.216-222
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  • 2017
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Si1-xGex Positive Feedback Field-effect Transistor with Steep Subthreshold Swing for Low-voltage Operation

  • Hwang, Sungmin (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Kim, Hyungjin (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Kwon, Dae Woong (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Lee, Jong-Ho (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Park, Byung-Gook (Department of Electrical and Computer Engineering, Seoul National University)
  • 투고 : 2016.08.24
  • 심사 : 2016.11.01
  • 발행 : 2017.04.30
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초록

The most prominent challenge for MOSFET scaling is to reduce power consumption; however, the supply voltage ($V_{DD}$) cannot be scaled down because of the carrier injection mechanism. To overcome this limit, a new type of field-effect transistor using positive feedback as a carrier injection mechanism (FBFET) has been proposed. In this study we have investigated the electrical characteristics of a $Si_{1-x}Ge_x$ FBFET with one gate and one-sided $Si_3N_4$ spacer using TCAD simulations. To reduce the drain bias dependency, $Si_{1-x}Ge_x$ was introduced as a low-bandgap material, and the minimum subthreshold swing was obtained as 2.87 mV/dec. This result suggests that a $Si_{1-x}Ge_x$ FBFET is a promising candidate for future low-power devices.

키워드

참고문헌

  1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, Vol. 89, No. 3, pp.259-288, Mar. 2001. https://doi.org/10.1109/5.915374
  2. K. P. Cheung, "On the 60 mV/dec @300 K limit for MOSFET subthreshold swing", Intl. Symp. VLSI Technol. Syst. Appl. (VLSI-TSA), pp. 72-73, Apr. 2010.
  3. W. Y. Choi, B.-G. Park, J. D. Lee, and T-J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Lett., Vol. 28, No. 8, pp.743-745, Aug. 2007. https://doi.org/10.1109/LED.2007.901273
  4. W. Wang, P-F. Wang, C-M. Chang, X. Lin, X-Y. Liu, Q-Q. Sun, P. Zhou, and D. W. Zhang, "Design of U-Shape Channel Tunnel FETs With SiGe Source Regions," IEEE Trans. Electron Devices, Vol. 61, No. 1, pp.193-197, Jan. 2014. https://doi.org/10.1109/TED.2013.2289075
  5. H. Kim, and B.-G. Park, "A 1T-DRAM cell based on a tunnel field-effect transistor with highly-scalable pillar and surrounding gate structure," Journal of the Korean Physical Society, Vol. 69, No. 3, pp. 323-327, Aug. 2016. https://doi.org/10.3938/jkps.69.323
  6. S. W. Kim, M.-C Sun, E. Park, J. H. Kim, D. W. Kwon and B.-G. Park, "Improvement of current drivability in highscalable tunnel field-effect transistors with CMOS compatible self-aligned process," Electronics Lett., Vol. 52, No. 12, pp. 1071-1072, Jun. 2016. https://doi.org/10.1049/el.2016.0707
  7. D. W. Kwon, J. H. Kim, E. Park, J. Lee, T. Park, R. Lee, S. Kim, and B.-G. Park, "Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain," Japanese Journal of Applied Physics, Vol. 55, No. 6S1, pp. 06GG04-1-06GG04-4, Jun. 2016. https://doi.org/10.7567/JJAP.55.06GG04
  8. S. W. Kim, J. H. Kim, T.-J. K. Liu, W. Y. Choi, and B.-G. Park, "Demonstration of L-Shaped Tunnel Field-Effect Transistors," IEEE Trans. on Electron Devices, Vol. 63, No. 4, pp. 1774-1778, Apr. 2016. https://doi.org/10.1109/TED.2015.2472496
  9. J. H. Kim, S. W. Kim, H. W. Kim, and B.-G. Park, "Vertical type double gate tunnelling FETs with thin tunnel barrier," Electronics Lett., Vol. 51, No. 9, pp. 718-720, Apr. 2015. https://doi.org/10.1049/el.2014.3864
  10. P.-Y. Wang and B.-Y. Tsui, "Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio," IEEE Electron Device Lett., Vol. 36, No. 12, Dec. 2015.
  11. C. Wu, R. Huang, Q. Huang, J. Wang, and Y. Wang, "Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior," IEEE Electron Device Lett., Vol. 37, No. 1, Jan. 2016.
  12. P. Long, J. Z. Huang, M. Povolotskyi, G. Klimeck, and M. J. W. Rodwell, "High-Current Tunneling FETs With (110) Orientation and a Channel Heterojunction," IEEE Electron Device Lett., Vol. 37, No. 3, Mar. 2016.
  13. F. J. Garcia-Sanchez, A. Ortiz-Conde, J. Muci, and A. S. Gonzalez, "Systematic Characterization of Tunnel FETs Using a Universal Compact Model," IEEE Trans. on Electron Devices, Vol. 62, No. 11, Nov. 2015.
  14. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "Impact ionization MOS (I-MOS)-Part I: device and circuit simulations," IEEE Trans. Electron Devices, Vol. 52, No. 1, pp. 69-76, Jan. 2005. https://doi.org/10.1109/TED.2004.841344
  15. M. J. Kumar, M. Maheedhar, and P. P. Varma, "Bipolar I-MOS-An Impact-Ionization MOS With Reduced Operating Voltage Using the Open-Base BJT Configuration," IEEE Trans. on Electron Devices, Vol. 62, No. 12, Dec. 2015.
  16. S. Ramaswamy and M. J. Kumar, "Junctionless Impact Ionization MOS: Proposal and Investigation," IEEE Trans. on Electron Devices, Vol. 61, No. 12, Dec. 2014.
  17. A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T-S. K. Liu, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages," IEEE Int. Electron Devices Meeting Tech. Dig., pp. 1-4, Dec. 2008.
  18. C. W. Yeung, A. Padilla, T-S. K. Liu, and C. Hu, "Programming Characteristics of the Steep Turn-on/off Feedback FET (FBFET)," Symposium on VLSI Technology, pp. 176-177, 2009.
  19. Y. Jeon, M. Kim, D. Lim, and S. Kim, "Steep Subthreshold Swing n-and p-Channel Operation of Bendable Feedback Field-Effect Transistors with $p^+-i-n^+$ Nanowires by Dual-Top-Gate Voltage Modulation," Nano Lett., Vol. 15, No. 8, pp.4905-4913, July. 2015. https://doi.org/10.1021/acs.nanolett.5b00606
  20. Y. Taur and T. H. Ning, "Fundamentals of modern VLSI devices," Cambridge university press, 2009.
  21. M. E. Levinshtein, S. L. Rumyantsev, and M. S. Shur, "Properties of Advanced Semiconductor Materials GaN, AlN, InN, BN, SiC, SiGe," John Wiley & Sons, Inc., 2001.

피인용 문헌

  1. High On-Current Ge-Channel Heterojunction Tunnel Field-Effect Transistor Using Direct Band-to-Band Tunneling vol.10, pp.2, 2019, https://doi.org/10.3390/mi10020077