한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제21권3호
  • /
  • Pages.594-600
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  • 2017
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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고성능 HEVC 부호기를 위한 움직임추정 하드웨어 설계

The Design of Motion Estimation Hardware for High-Performance HEVC Encoder

  • Park, Seungyong (Department of Information and Communication Engineering, Hanbat National University) ;
  • Jeon, Sunghun (Department of Information and Communication Engineering, Hanbat National University) ;
  • Ryoo, Kwangki (Department of Information and Communication Engineering, Hanbat National University)
  • 투고 : 2017.01.09
  • 심사 : 2017.01.26
  • 발행 : 2017.03.31
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초록

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 부호기를 위한 전역탐색 기반의 움직임추정 알고리즘과 이에 적합한 하드웨어 구조를 제안한다. HEVC 화면 간 예측에서의 움직임추정은 시간적 중복성을 제거하기 위하여 보간 된 참조 픽쳐에서 현재 PU와 상관도가 높은 예측 블록을 탐색하는 과정으로 전역탐색 알고리즘과 고속탐색 알고리즘을 이용한다. 전역 탐색 기법은 주어진 탐색 영역내의 모든 후보 블록에 대하여 움직임을 예측하기 때문에 최적의 결과를 보장하지만 연산량 및 연산시간이 많은 단점을 지닌다. 그러므로 본 논문에서는 Inter Prediction의 연산량 및 연산시간을 줄이기 위해 전역탐색에서 SAD연산을 재사용하여 연산복잡도를 줄이는 새로운 알고리즘을 제안하고 이에 적합한 하드웨어 구조를 제안한다. 제안된 알고리즘은 HEVC 표준 소프트웨어 HM16.12에 적용하여 검증한 결과 기존 전역탐색 알고리즘보다 연산시간은 61%, BDBitrate는 11.81% 감소하였고, BDPSNR은 약 0.5% 증가하였다. 또한 하드웨어설계 결과 최대 동작주파수는 255 Mhz, 총 게이트 수는 65.1K 이다.

This paper proposes a global search based motion estimation algorithm for high performance HEVC encoder and its hardware architecture. To eliminate temporal redundancy, motion estimation in HEVC inter-view prediction uses global search and fast search algorithm to search for a predicted block having a high correlation with the current PU in an interpolated reference picture. The global search method predicts the motion of all candidate blocks in a given search area, thus ensuring optimal results, but has a disadvantage of large computation time. Therefore we propose a new algorithm that reduces computational complexity by reusing SAD operation in global search to reduce computation time of inter prediction. As a result of applying the proposed algorithm to standard software HM16.12, the computation time was reduced by 61%, BDBitrate by 11.81%, and BDPSNR by about 0.5% compared with the existing search algorithm. As a result of hardware design, the maximum operating frequency is 255 MHz and the total number of gates is 65.1K.

키워드

참고문헌

  1. H. Jung, and K. Ryoo, "An Intra Prediction Hardware Architecture Design for Computational Complexity Reduction of HEVC Decoder," Journal of the Korea Institute of Information and Communication Engineering, vol. 17, no. 5, pp. 1203-1212, May 2013. https://doi.org/10.6109/jkiice.2013.17.5.1203
  2. S. Park, H. Jo, and K. Ryoo, "The Design of Transform and Quantization Hardware for High-Performance HEVC Encoder," Journal of the Korea Institute of Information and Communication Engineering, vol. 20, no. 2, pp.327-334, Feb. 2016. https://doi.org/10.6109/jkiice.2016.20.2.327
  3. N. Purnachand, L. N. Alves, and A. Navarro, "Improvements to TZ search motion estimation algorithm for multiview video coding," in International Conference on System Signals and Image Processing(IWSSIP) 19th, Apr. 2012.
  4. J. Zhang, B. Li, and H. Li, "An Efficeient Fast Mode Decision Method for Inter Prediction in HEVC," IEEE Transactions Circuits System Video Technology, vol. 26, no. 8, pp. 1502-1515, Aug. 2015. https://doi.org/10.1109/TCSVT.2015.2461991
  5. S. Ahn, M. Kim, and S. Park. "Fast decision of CU partitioning based on SAO parameter, motion and PU/TU split information for HEVC," in Proceeding of Picture Coding Symposium, pp. 113-116. Dec. 2013.
  6. F. Sampaio, S. Bampi, M. Grellert, L. Agostini, and J. Mattos, "Motion vectors merging: low complexity prediction unit decision heuristic for the inter-prediction of HEVC encoders," in IEEE International Conference on Multimedia and Expo (ICME), pp. 657-662, July. 2012.
  7. Z. Liu, S. Goto, and T. Ikenaga, "Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264," IEEE International Conference on Computer Design, pp. 328-333, Oct. 2008.
  8. P. Nalluri, L. N. Alves, and A. Navarro, "High Speed SAD Architectures for Variable block size Motion Estimation In HEVC Video Coding," in Proceeding. IEEE International Conference on ICIP Circuits, pp. 1233- 1237, Oct. 2014.