Journal of Power Electronics

  • 제17권2호
  • /
  • Pages.346-357
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  • 2017
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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A Fast Sorting Strategy Based on a Two-way Merge Sort for Balancing the Capacitor Voltages in Modular Multilevel Converters

  • Zhao, Fangzhou (State Key Laboratory of Electrical Insulation and Power Equipment, School of Electrical Engineering, Xi'an Jiaotong University) ;
  • Xiao, Guochun (State Key Laboratory of Electrical Insulation and Power Equipment, School of Electrical Engineering, Xi'an Jiaotong University) ;
  • Liu, Min (State Key Laboratory of Electrical Insulation and Power Equipment, School of Electrical Engineering, Xi'an Jiaotong University) ;
  • Yang, Daoshu (State Key Laboratory of Electrical Insulation and Power Equipment, School of Electrical Engineering, Xi'an Jiaotong University)
  • 투고 : 2016.09.11
  • 심사 : 2016.12.30
  • 발행 : 2017.03.20
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초록

The Modular Multilevel Converter (MMC) is particularly attractive for medium and high power applications such as High-Voltage Direct Current (HVDC) systems. In order to reach a high voltage, the number of cascaded submodules (SMs) is generally very large. Thus, in the applications with hundreds or even thousands of SMs such as MMC-HVDCs, the sorting algorithm of the conventional voltage balancing strategy is extremely slow. This complicates the controller design and increases the hardware cost tremendously. This paper presents a Two-Way Merge Sort (TWMS) strategy based on the prediction of the capacitor voltages under ideal conditions. It also proposes an innovative Insertion Sort Correction for the TWMS (ISC-TWMS) to solve issues in practical engineering under non-ideal conditions. The proposed sorting methods are combined with the features of the MMC-HVDC control strategy, which significantly accelerates the sorting process and reduces the implementation efforts. In comparison with the commonly used quicksort algorithm, it saves at least two-thirds of the sorting execution time in one arm with 100 SMs, and saves more with a higher number of SMs. A 501-level MMC-HVDC simulation model in PSCAD/EMTDC has been built to verify the validity of the proposed strategies. The fast speed and high efficiency of the algorithms are demonstrated by experiments with a DSP controller (TMS320F28335).

키워드

참고문헌

  1. A. Lesnicar and R. Marquardt, "An innovative modular ltilevel converter topology suitable for a wide power range," in Proc. IEEE Bologna Power Tech Conference, pp. 1-6, 2003.
  2. M. Saeedifard and R. Iravani, "Dynamic performance of a modular multilevel back-to-back HVDC system," IEEE Trans. Power Deliv., Vol. 25, No. 4, pp. 2903-2912, Oct. 2010. https://doi.org/10.1109/TPWRD.2010.2050787
  3. J. Peralta, H. Saad, S. Dennetiere, J. Mahseredjian, and S. Nguefeu, "Detailed and averaged models for a 401-level MMC-HVDC system," IEEE Trans. Power Deliv., Vol. 27, No. 3, pp. 1501-1508, Jul. 2012. https://doi.org/10.1109/TPWRD.2012.2188911
  4. P. Liu, Y. Wang, W. Cong, and W. Lei, "Grouping-Sorting-Optimized Model Predictive Control for Modular Multilevel Converter with Reduced Computational Load," IEEE Trans. Power Electron., Vol. 31, No. 3, pp. 1896-1907, Mar. 2015. https://doi.org/10.1109/TPEL.2015.2432767
  5. Q. Tu, Z. Xu, H. Huang, and J. Zhang, "Parameter design principle of the arm inductor in modular multilevel converter based HVDC," in Conference on Power System Technology, pp. 1-6, 2010
  6. U. N. Gnanarathna, A. M., Gole, and R. P., Jayasinghe, "Efficient modeling of modular multilevel HVDC converters (MMC) on electromagnetic transient simulation programs," IEEE Trans. Power Deliv., Vol. 26, No. 1, pp. 316-324, Jan. 2011. https://doi.org/10.1109/TPWRD.2010.2060737
  7. S. Debnath, J. Qin, B. Bahrani, M. Saeedifard, and P. Barbosa, "Operation, control, applications of the modular multilevel converter: A review," IEEE Trans. Power Electron., Vol. 30, No. 1, pp. 37-53, Jan. 2015. https://doi.org/10.1109/TPEL.2014.2309937
  8. M. Hagiwara and H. Akagi, "Control and experiment of pulsewidth modulated modular multilevel converters," IEEE Trans. Power Electron., Vol. 24, No. 7, pp. 1737-1746, Jul. 2009. https://doi.org/10.1109/TPEL.2009.2014236
  9. J. Mei, K. Shen, B. Xiao, L. M. Tolbert, and J. Zheng, "A new selective loop bias mapping phase disposition PWM with dynamic voltage balance capability for modular multilevel converter," IEEE Trans. Ind. Electron., Vol. 61, No. 2, pp. 798-807, Feb. 2014 https://doi.org/10.1109/TIE.2013.2253069
  10. F. Deng and Z. Chen, "A control method for voltage balancing in modular multilevel converters," IEEE Trans. Power Electron., Vol. 29, No. 1, pp. 66-76, Jan. 2014. https://doi.org/10.1109/TPEL.2013.2251426
  11. J. Qin and M. Saeedifard, "Predictive control of a modular multilevel converter for a back-to-back HVDC system," IEEE Trans. Power Deliv., Vol. 27, No. 3, pp. 1538-1547, Jul. 2012. https://doi.org/10.1109/TPWRD.2012.2191577
  12. P. M. Meshram and V. B. Borghate, "A Simplified Nearest Level Control (NLC) Voltage Balancing Method for Modular Multilevel Converter (MMC)," IEEE Trans. Power Electron., Vol. 30, No. 1, pp. 450-462, Jan. 2015. https://doi.org/10.1109/TPEL.2014.2317705
  13. S. Rohner, S. Bernet, M. Hiller, and R. Sommer, "Modelling, simulation and analysis of a modular multilevel converter for medium voltage applications," in IEEE Conference on Industrial Technology, pp. 775-782, 2010
  14. S. Rohner, S. Bernet, M. Hiller, and R. Sommer, "Modulation, losses, and semiconductor requirements of modular multilevel converters," IEEE Trans. Ind. Electron., Vol. 57, No. 8, pp. 2633-2642, Aug. 2010. https://doi.org/10.1109/TIE.2009.2031187
  15. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to algorithms, 3th ed., MIT Press, Chap. 2, pp. 147-212, 2001.
  16. J. Qin and M. Saeedifard, "Reduced switching-frequency voltage balancing strategies for modular multilevel HVDC converters," IEEE Trans. Power Deliv., Vol. 28, No. 4, pp. 2403-2410, Oct. 2013. https://doi.org/10.1109/TPWRD.2013.2271615
  17. K. Ilves, L. Harnefors, S. Norrga, and H.-P. Nee, "Predictive sorting algorithm for modular multilevel converters minimizing the spread in the submodule capacitor voltages," IEEE Trans. Power Electron., Vol. 30, No. 1, pp. 440-449, Jan. 2015. https://doi.org/10.1109/TPEL.2014.2308018
  18. Q. Tu, Z. Xu, and L. Xu, "Reduced switching-frequency modulation and circulating current suppression for modular multilevel converters," IEEE Trans. Power Deliv., Vol. 26, No. 3, pp. 2009-2017, Jul. 2011. https://doi.org/10.1109/TPWRD.2011.2115258
  19. D. Siemaszko, "Fast sorting method for balancing capacitor voltages in modular multilevel converters," IEEE Trans. Power Electron., Vol. 30, No. 1, pp. 463-470, Jan. 2015. https://doi.org/10.1109/TPEL.2014.2312101
  20. J. Xu, C. Zhao, and A. M. Gole, "Research on the Thevenin's equivalent based integral modelling method of the modular multilevel converter," Proc. of the CSEE., Vol. 35, No. 8, pp. 1919-1929, Apr. 2015.
  21. L. Wei, L. A. Gregoire, and J. Belanger: "A modular multilevel converter pulse generation and capacitor voltage balance method optimized for FPGA implementation," IEEE Trans. Ind. Electron., Vol. 62, No. 5, pp. 2859-2867, May. 2015. https://doi.org/10.1109/TIE.2014.2362879
  22. F. Zhao, G. Xiao, Z. Song, and C. Peng, "Insertion sort correction of two-way merge sort algorithm for balancing capacitor voltages in MMC with reduced computational load," in Proc. IPEMC, pp. 748-753, May. 2016.
  23. D. Knuth, Art of computer programming, volume 3: Sorting and Searching, 3th ed., Addison-Wesley, Chap. 5, pp. 158-166, 2011.

피인용 문헌

  1. Accurate Steady-State Mathematical Models of Arm and Line Harmonic Characteristics for Modular Multilevel Converter vol.33, pp.3, 2018, https://doi.org/10.1109/TPWRD.2017.2764950