Nuclear Engineering and Technology

  • 제49권8호
  • /
  • Pages.1589-1599
  • /
  • 2017
  • /
  • 1738-5733(pISSN)
  • /
  • 2234-358X(eISSN)
한국원자력학회 (Korean Nuclear Society)
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Understanding radiation effects in SRAM-based field programmable gate arrays for implementing instrumentation and control systems of nuclear power plants

  • Nidhin, T.S. (Indira Gandhi Centre for Atomic Research, Homi Bhabha National Institute) ;
  • Bhattacharyya, Anindya (Indira Gandhi Centre for Atomic Research, Homi Bhabha National Institute) ;
  • Behera, R.P. (Indira Gandhi Centre for Atomic Research, Homi Bhabha National Institute) ;
  • Jayanthi, T. (Indira Gandhi Centre for Atomic Research, Homi Bhabha National Institute) ;
  • Velusamy, K. (Indira Gandhi Centre for Atomic Research, Homi Bhabha National Institute)
  • 투고 : 2017.05.16
  • 심사 : 2017.09.16
  • 발행 : 2017.12.25
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초록

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

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