International Journal of Internet, Broadcasting and Communication

  • 제8권1호
  • /
  • Pages.42-52
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  • 2016
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  • 2288-4920(pISSN)
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  • 2288-4939(eISSN)
한국인터넷방송통신학회 (The Institute of Internet, Broadcasting and Communication)
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Optimization of ARIA Block-Cipher Algorithm for Embedded Systems with 16-bits Processors

  • Lee, Wan Yeon (Dept. of Computer Science, Dongduk Women's University) ;
  • Choi, Yun-Seok (Dept. of Computer Science, Dongduk Women's University)
  • 투고 : 2015.12.07
  • 심사 : 2016.01.08
  • 발행 : 2016.02.29
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초록

In this paper, we propose the 16-bits optimization design of the ARIA block-cipher algorithm for embedded systems with 16-bits processors. The proposed design adopts 16-bits XOR operations and rotated shift operations as many as possible. Also, the proposed design extends 8-bits array variables into 16-bits array variables for faster chained matrix multiplication. In evaluation experiments, our design is compared to the previous 32-bits optimized design and 8-bits optimized design. Our 16-bits optimized design yields about 20% faster execution speed and about 28% smaller footprint than 32-bits optimized code. Also, our design yields about 91% faster execution speed with larger footprint than 8-bits optimized code.

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참고문헌

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