JSTS:Journal of Semiconductor Technology and Science

  • 제16권5호
  • /
  • Pages.635-640
  • /
  • 2016
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

A Recessed-channel Tunnel Field-Effect Transistor (RTFET) with the Asymmetric Source and Drain

  • Kwon, Hui Tae (Department of Nanoenergy Engineering, College of Nanoscience and Nanotechnology, Pusan National University) ;
  • Kim, Sang Wan (Department of Electrical Engineering and Computer Sciences, University of California) ;
  • Lee, Won Joo (Department of Nanoenergy Engineering, College of Nanoscience and Nanotechnology, Pusan National University) ;
  • Wee, Dae Hoon (Department of Nanoenergy Engineering, College of Nanoscience and Nanotechnology, Pusan National University) ;
  • Kim, Yoon (Department of Nanoenergy Engineering, College of Nanoscience and Nanotechnology, Pusan National University)
  • 투고 : 2016.01.28
  • 심사 : 2016.05.10
  • 발행 : 2016.10.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

키워드

참고문헌

  1. Q. Huang et al, "Comprehensive performance reassessment of TFETs with a novel design by gate and source engineering from device/circuit perspective," Proc. IEDM, 2014, pp. 13.3.1-13.3.4.
  2. Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Design Guideline of Si-Based L-shaped Tunneling Field-Effect Transistors", Jpn. J. Appl. Phys., vol. 51, no. 6S, 06FE09-1-06FE09-4, 2012. https://doi.org/10.7567/JJAP.51.06FE09
  3. Sang Wan Kim, Jang Hyun Kim, Tsu-Jae King Liu, Woo Young Choi, and Byung-Gook Park, "Demonstration of L-shaped Tunnel Field-Effect Transistors", Electron Devices, IEEE Transactions on, Vol. PP, Issue 99., 2015.
  4. Woo Young Choi, Byung-Gook Park, Jong Duk Lee, and Tsu-Jae King Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (S) less than 60 mV/dec," Electron Device Letters, IEEE, vol. 28, no. 8, pp. 743-745, Aug. 2007. https://doi.org/10.1109/LED.2007.901273
  5. Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, "Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications", J. Semicond. Technol. Sci., Vol. 12, No. 4, pp. 482-489, Dec., 2012. https://doi.org/10.5573/JSTS.2012.12.4.482
  6. A. Chattopadhyay and A. Mallik, "Impact of a spaer dielectric and gate overlap/underlap on the device performance of a tunnel field-effect transistor," Electron Devices, IEEE Transactions on, Vol. 58, No. 3, pp. 677-683, Mar. 2011. https://doi.org/10.1109/TED.2010.2101603
  7. S. Takagi, M. Kim, M. Noguchi, S.-M. Ji, K. Nishi, and M. Takenaka, "III-V and Ge/strained SOI tunneling FET technologies for low power LSIs," VLSI Tech. Dig., 2015, pp. 22-23.
  8. G. Dewey et al, "Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing," Proc. IEDM , 2011, pp. 33.6.1-33.6.4.
  9. Y. Morita et al, "Synthetic electric field tunnel FETs: Drain current multiplication demonstrated by wrapped gate electrode around ultrathin epitaxial channel," VLSI Tech. Dig., 2013, pp. T236-T237.