A New Interleaved Double-Input Three-Level Boost Converter

Abstract

This paper proposes a new interleaved double-input three-level Boost (DITLB) converter, which is composed of two boost converters indirectly in series. Thus, a high voltage gain, together with a low component stress and a small input current ripple due to the interleaved control scheme, is achieved. The operating principle of the DITLB converter under the individual supplying power (ISP) and simultaneous supplying power (SSP) mode is analyzed. In addition, closed-loop control strategies composed of a voltage-current loop and a voltage-balance loop, have been researched to make the converter operate steadily and to alleviate the neutral-point imbalance issue. Experimental results verify correctness and feasibility of the proposed topology and control strategies.

I. INTRODUCTION

In a renewable power generation system with many different input sources, many individual dc-dc converters together with independent control schemes are necessary, which are both complex and increase the cost of the system. Integrating different input sources with distinct electrical characteristics into a common system while still achieving a high efficiency and good performance is an important topic. To attain the goal of integration, a multi-input converter (MIC) is a perfect choice, which may integrate diverse power sources and provide power to a common load in a single conversion stage [1].

Many papers related to a variety of MIC topologies have been published. In [2], a systematic approach to synthesizing MICs by introducing pulsating voltage source cells and pulsating current source cells into six basic PWM converters is proposed. Four rules that must be observed in order to realize a MIC from its single-input version are listed in [3]. In renewable power generation systems, MIC topologies are usually integrated with a dc link. However, most of these MICs do not take the high voltage gain into consideration, since the outputs of photovoltaic cells, fuel cells and battery cells are typically unregulated low-level dc voltages that need to be stepped up to regulated, high-level voltages for practical applications.

At present, the conventional Boost converter is usually used because of its simple circuit. Unfortunately, practical considerations limit its output voltage to about four times its input voltage [4]. To increase the voltage gain and achieve other performances, many high step-up converter topologies have been proposed. A high step-up active-clamp converter composed of an input current doubler and a symmetrical switched-capacitor circuit is proposed in [5]. Although a high voltage gain is achieved, many switches are needed. Several high set-up converter topologies that use coupled inductors have been proposed for the fuel cell generation systems [6], [7]. Although a high voltage gain is obtained, their efficiencies are degraded due to the losses associated with leakage inductances. In addition, coupled inductors may introduce high switch voltage stress and EMI problems.

Recently, some step-up dc–dc converters have been studied. However, but they are limited to single-input-single-output systems [8]-[10]. The system structure of a conventional three-level Boost converter (CTLB) combined with a three-level diode-clamped inverter has been proposed to achieve a high medium voltage and a high power. In addition, a small input current ripple and a neutral-point voltage control can be achieved [11]-[13]. However, the step-up capacity of the systems is limited due to the CTLB converter, which is only 1/(1-D). A novel hybrid three-level Boost (HTLB) converter had been proposed to achieve a high voltage gain at the expense of increasing the number of components and the addition of a complex modulation strategy [14]. [15], [16] propose a series of multilevel boost converters based on switched-capacitor networks, which have high voltage gains and a self-balance function for capacitor voltages. In addition, the self-balance function is highly advantageous for balancing the dc link capacitor voltages of diode-clamped multilevel inverters [17], [18]. However, since no interleaved scheme is adopted, the input current ripple and the current stress of a single switch are both very large, which are great disadvantages for FC and BC systems. [19] proposes a three-level Boost converter with a flying-capacitor (FCTLB) and [20] transforms this converter into a multi-input converter. Although a high voltage gain and small ripples are achieved, the voltage stresses across the output diode are high. In addition, two double-input converters operating in the ISP mode and in the SSP mode are proposed with a high voltage gain and small component stresses [21]. However, it is difficult to integrate the two converters, and many capacitors are necessary.

On the whole, multi-input step-up converters are essential for integrating different energy sources with low voltage levels. The development of multi-input step-up converter topologies goes through three stages, as shown in Fig.1. In Fig. 1(a), a MIC structure is constructed by placing several step-up converters in parallel with all of the output terminals. However, the output voltage gain is limited due to its parallel structure. Then, the MIC structure shown in Fig. 1(b) is proposed by placing the output terminals in series. However, the input terminals and output terminals usually do not share the same ground, which may introduce an electro-magnetic interference (EMI) problem and increase the quantity of isolated power drivers. Therefore, the MIC structure shown in Fig. 1(c) should be the best choice to alleviate the above mentioned problems. This structure has a high voltage gain since the output terminals are directly or indirectly connected in series. In addition, the input terminals and output terminals have a common ground, which helps reduce EMI and cost of driver circuits. Additionally, an interleaved control scheme can be easily adopted to decrease the input current ripple.

Fig. 1.The development of multi-input step-up converters.

In this paper, a new DITLB converter is proposed that can operate under the individual supplying power (ISP) mode and the simultaneous supplying power (SSP) mode. A small input current ripple, low current stresses and low voltage stresses across all of the power devices are achieved. Additionally, the self-balance function for capacitor voltages is included. This paper is organized as follows: Section II introduces the operation principle of the proposed converter. A performance analysis is subsequently presented in Section III. A closed-loop control strategy for the proposed DITLB converter under different operating modes has been presented in Section IV, and experimental verification is presented in Section V. Finally, some conclusion have been drawn in Section VI.

 

II. THE PROPOSED DITLB CONVERTER

The proposed DITLB converter is presented in Fig. 2. To analyze the converter, the converter is divided into three cells: cell 1, cell 2, and cell 3. Cell 1 (including L1, S1, D1, and C1) and cell 2 (including L2, S2, D3, and C2) are Boost converters. Cell 3 is composed of C3 and D2, and connects the two Boost converters in series. Therefore, the operating principle of the DITLB under the continuous conduction mode (CCM) is different from that of two Boost converters directly in series. The proposed converter is controlled by the interleaved operation scheme of S1 and S2, where the two carrier signals Ca1 and Ca2 have a phase shift of 180 degrees. To simplify the analysis process, some assumptions are made as follows:

Fig. 2.The proposed DITLB converter.

1) The inductor currents iL1 and iL2 and the input current iin are continuous, and their average values are labelled as IL1, IL2, and Iin.

2) uL1 and uL2 represent the voltages across L1 and L2, and UC1, UC2, and UC3 represent the capacitor voltages of C1, C2, and C3.

3) All of the components are ideal without considering any parasitic parameters.

According to the definition of a MIC, the proposed converter works under both the ISP mode and the SSP mode. In Fig. 2, the turn-on and turn-off of Q1, Q2, and Q3 determine the operating mode. When Q1, and Q3 are turned on while Q2 is turned off, the DITLB converter operates under the ISP mode with input source 1 supplying power. In addition, when Q2 and Q3 are turned on while Q1 is turned off, the DITLB converter operates under the ISP mode with input source 2 supplying power. However, when Q1 and Q2 are turned on while Q3 is turned off, the DITLB converter operates under the SSP mode with the two input sources supplying power simultaneously.

A. Operating Principle under ISP Mode

Under the ISP mode, the two switches S1 and S2 in the DITLB converter are controlled by an interleaved operation scheme with the same duty cycle D. Since the converter operates under the same operating principle regardless of which input source is used, the ISP mode with input source 1 is taken as an example for the theoretical analysis. Equivalent circuits of the converter under this mode are shown in Fig.3 and typical waveforms are given in Fig.4. The basic operating principle is presented as follows.

Fig. 3.Equivalent circuits of the DITLB converter under ISP mode with input source 1 supplying power:

Fig. 4.Typical waveforms.

Stage I: during this period, L1 and L2 are both charged by Uin1. The conduction of S1 and D2 provides a pathway for C2 and C3 to be connected in parallel. Thus, the following expressions can be achieved:

Stage II: during this period, L1 is still charged by Uin1. Additionally, C2 is still in parallel with C3, which is charged by L2 and Uin1. Thus, the voltage across L2 is changed by:

Stage III: during this period, L2 is charged by Uin1 and the same formula (2) can be obtained. However, the voltage across L1 is described by:

(5) can be simplified by combining (3):

Stage IV: during this period, the voltage across L1 is the same as (6). In addition, C3 is charged by L2 and Uin1. Thus, the voltage across L2 is the same as (4).

In all four stages, the output voltage of the converter is the sum of UC1 and UC2. Since the two Boost converters are indirectly in series, i.e.:

According to the interleaved operation scheme, the converter can operate under two conditions: D>0.5 and D<0.5. When the duty cycle D is bigger than 0.5, it operates at the periodic stages of I, II, I, and III. Accoding to (1)-(5) and (7), voltage gain and capacitor voltages can be achieved:

It can be seen from (9) that the three capacitor voltages are equal. It should be noted that UC2 and UC3 are self-balanced due to the switched-capacitor network, while UC1 and UC2 are balanced since they have the same duty cycle D. On the whole, it is called self-voltage-balance function.

Additionally, the current ripples of L1 and L2 shown in Fig. 4, can be obtained as follows:

At the same time, it is easy to obtain the input current ripple:

When the duty cycle D is smaller than 0.5, the proposed converter operates at the periodic stages of IV, II, IV, and III; and the same results shown in (8)-(10) can be achieved. Under this operating state, the input current ripple is changed by:

Regardless of the duty cycle D, stages II and III have the same operating time. At stage II, the capacitor C3 is charged by Uin1 and L2 with the current IL2. Meanwhile, at stage III, C3 discharges energy to the load with the current IL1. According to the Ampere-Second Balance Principle for C3, it is not difficult to conclude that IL1 is equal to IL2. This is called self-current-balance function. Then, based on the Power Conservation Principle, there is:

(13) can be simplified by combining (8):

It should be note that similar results can be achieved when the converter operates under the ISP mode with input source 2.

It is well known that the discontinuous conduction mode (DCM) occurs when the inductor current ripple becomes greater than the average inductor current. Since cell 1 and cell 2 have the same inductance, the inductor L2 is taken as an example:

The integration of (8), (10) and (14) into (15) yields the following condition for the DCM mode:

Where K is equal to 2Lfs/R, and Kcrit(D) is the critical value of K at the boundary between the CCM and DCM modes:

The maximum value of Kcrit(D) can be easily achieved at D = 1/3.

If K is greater than 2/27, the converter operates under the CCM mode for all values of D. If K is smaller than 2/27, the converter operates under the DCM mode for some intermediate range values of D near D=1/3. Thus, the minimum inductance Lmin should be:

(19) is simplified to achieve Lmin as follows:

B. Operating Principle under SSP Mode

When Q1 and Q2 turn on while Q3 turns off, the proposed DITLB converter operating under the SSP mode is shown in Fig. 5. Under this mode, cell 1 and cell 2 operate independently, i.e. cell 1 does not affect cell 2. In addition, the two cells are controlled by two independent closed-loop control strategies. It should be noted that the converter does not need to operate with an interleaved operation scheme, since the two input sources feed the load simultaneously. Thus, it is not difficult to obtain the output voltage and capacitor voltages as follows:

The two average inductor currents can be described by:

Fig. 5.The DITLB converter operates under SSP mode.

 

III. CLOSED-LOOP CONTROL STRATEGY

As analyzed in section II, the proposed DITLB converter under the ISP mode has a voltage-balance function for the capacitor voltages. However, like three-level Boost converters, the converter also has a neutral-point balancing problem due to the interleaved operation scheme. In addition, the IGBTs and power diodes usually have some voltage drops, which should be considered in practical circuit design. If Ud is assumed to be the voltage drops, two voltage-second equations can be rewritten by:

Then, the output voltage and capacitor voltages can be achieved based on (26) and (27):

The voltage difference between C1 and C2 can be obtained based on (29) and (30)

It can be seen from (31) that there is a voltage difference 2Ud between C1 and C2 due to the voltage drops. Although it is small, the voltage drops may result in a neutral-point balancing problem.

A Closed-loop Control under ISP Mode

To alleviate the neutral-point problem of the proposed converter under the ISP mode, a voltage-current loop together with a simple voltage-balance loop is presented in Fig. 6.

Fig. 6.Closed-loop control strategy under ISP mode.

As analyzed in section II, cell 1 and cell 2 represent two Boost converters, whose output terminals are connected in series. In addition, the two Boost converters are controlled by an interleaved scheme with the same duty cycle D. Thus, the same average inductor current and output capacitor voltage can be achieved. By only controlling one of the Boost converters, the input current and output voltage of the converter can be easily controlled to be stable. In Fig. 6, cell 2 is taken as the target to be controlled by voltage-current loop 2. By controlling the capacitor voltage UC2 and the inductor current IL2, it is easy to get the duty cycle d2 of S2.

The voltage-balance loop aims at reducing the voltage difference between C1 and C2. In the voltage-balance loop, the difference duty cycle Δd is achieved through a simple PI controller by the difference voltage ΔU . Then, the duty cycle d1 of the switch S1 can be easily obtained by:

From (32), the voltage-balance process is: when UC2 is bigger than UC1, Δd becomes positive, which makes d1 a little bigger than d2. Then, UC1 increases to follow UC2, and is finally equal to UC2 after several switching periods. It should be noted that Δd is very small, since the voltage difference is very small. Thus, voltage-current loop 2 cannot be greatly affected.

B Closed-loop Control under SSP Mode

Under the SSP mode, the two Boost converters are controlled independently by voltage-current loop 1 and voltage-current loop 2, as shown in Fig. 7. The capacitor voltages are controlled to be equal by setting the same referring voltage for the two Boost converters, i.e. UC1* is equal to UC2*. Thus, there is no need to use a voltage-balance loop under this mode.

Fig. 7.Closed-loop control strategy under SSP mode.

 

IV. PERFORMANCE ANALYSIS

A. Comparative Analysis

For both the ISP and SSP modes, the voltage stresses across the two switches are equal and the voltage stresses across all of the diodes are also equal. They are given as follows:

UVPS and UVPD represent the voltage stresses across the switches and diodes, respectively.

Under the ISP mode, the average current stress across all of the diodes and two switches are equal, shown in (34) and (35):

IVPS and IVPD represents the current stresses across switches and diodes, respectively.

As given in Section I, the CTLB, HTLB, FCTLB, and SCTLB converters are conventional three-level Boost, hybrid three-level Boost, three-level Boost with a flying-capacitor, and three-level Boost with a switched-capacitor network, respectively. It should be noted that the SCTLB converter is one version of the multilevel Boost converters in [15-18]. Table I shows comparative results among the CTLB, HTLB, FCTLB, SCTLB, and the proposed TLB converters.

TABLE ICOMPARATIVE ANALYSIS AMONG CTLB, HTLB, FCTLB, SCTLB CONVERTERS AND PROPOSED TLB CONVERTER

In the four three-level Boost converters, the HTLB has the highest voltage gain when the modulation indexes ma and mb are set well. However, so many components are necessary and the modulation strategy is complex. The SCTLB has a high voltage gain and a self-voltage-balance function with its input and output sharing a common ground. However, the input current and current stress across only one switch is very large, since it cannot use an interleaved scheme. Although interleaved schemes are adopted, the CTLB has no self-voltage-balance or current-balance functions. More importantly, its input and output do not share the same ground and its voltage gain is limited to 1/(1-D). Compared with CTLB, HTLB, SCTLB converters, the converter FCTLB presents relatively good performances. However, the output diode and output capacitor have very high voltage stresses, which are equal to the output voltage. Furthermore, since the output capacitor of the FCTLB is not composed of two split capacitors and is independent from its input, it cannot achieve the self-voltage-balance function or the voltage-balance control. However, all of these issues in the CTLB, HTLB, FCTLB and SCTLB, can be mostly avoided in the proposed TLB. Firstly, small voltage stresses for all of the components are achieved because cell 1 and cell 2 are in series. Secondly, small current stresses for these components are also achieved due to the interleaved operation scheme. Moreover, the self-voltage-balance function and the self-current-balance function help make cell 1 and cell 2 have the same performances. Lastly, the input source and output terminal share a common ground. Thus, the driver circuit of S1 and S2 can share the same power supply, reducing the design cost of the drive circuits. On the whole, the proposed TLB is the best converter.

B. The Key Function of Cell 3

As analyzed in Section II, cell 1 and cell 2 in the proposed converter, are two Boost converters, which share the same input source with the outputs in series. This is similar to an input-serial-output-parallel (IPOS) dc/dc system, which is usually composed of isolated dc/dc converters. However, unlike an IPOS dc/dc system, the proposed converter is composed of non-isolated dc/dc converters owing to cell 3. Because of cell 3 and S1, C2 constructs a switched-capacitor network that has the self-voltage-balance function. Therefore, the two capacitor voltages of C2 and C3 are easy to self-balanced when S1 is turned on, as shown in Fig. 3(a) and Fig. 3(b). In addition, this voltage-balance mechanism has been reported in [15]-[18]. Thus, a high voltage gain and a small input current ripple can be easily achieved. The voltage-balance mechanism for a converter under the ISP mode with Uin1 is: the energy of C3 comes from L1 and Uin1, and the energy of C2 comes from L2 and Uin1. Cell 1 and cell 2 can easily output the same capacitor voltage, since they are controlled by an interleaved scheme with the same duty cycle. Furthermore, the voltages of C3 and C2 are self-balanced due to the switched-capacitor network. Therefore, the voltages of C1, C2, and C3 are equal.

The voltage-balance mechanism for the converter under the ISP mode with Uin2 is the same as the above mentioned mechanism. On the whole, it is the key function of cell 3 that makes the proposed converter have a high voltage gain and the other good performances mentioned above.

C. Extension

Multi-input converters with more input sources and more output levels can be extended from the proposed DITLB converter. Fig. 8 shows the topology of an extended three-input four-level Boost converter, where there are three

Fig. 8.The three-input four-level Boost converter.

Boost converters: Uin1, S1, L1, D1, C1; Uin2, S2, L2, D3, C2; and Uin3, S3, L3, D5, C3.

A small input current and little current stress across every switch can be achieved. In addition, small voltage stresses 1/3Uo across all of the components besides C4, can be achieved. In the extended converter, besides the switched-capacitor network, is composed of S2 and C5. D4 and C3, are the components S1 and C4. D2, C2, and C3 form another switched-capacitor network. Thus, the voltage stress across C4 is 2/3Uo, which is the sum of UC2 and UC3.

When Q1, Q2, and Q3 are turned on and Q4 and Q5 are turned off, the converter operates under the SSP mode with all three input sources supplying power simultaneously. The output voltage under this mode can be given as follows:

In addition, the converter can also operate under the ISP mode with any two input sources. For instance, when Q2, Q3, and Q4 are turned on and Q1 and Q5 are turned off, the input sources Uin2 and Uin3 feed the load simultaneously. Under this mode, the output voltage is:

Under the ISP mode with only one input source supplying power, all three of the switches can be controlled by three interleaved drive signals, which are phase shifted 120 degrees. For example, when Q3 is turned on and Q1, Q2, Q4, and Q5 are turned off, the converter operates under the ISP mode with the input source Uin3. In addition, the output voltage under this mode can be descripted by:

As shown in Fig. 2 and Fig. 8, the proposed DITLB converter and the extended converter are a good choice to connect with Neutral-Point-Clamped (NPC) multilevel inverters to achieve a medium voltage and a high power. With this configuration, the capacitor voltages of the dc link can be controlled with the voltage-balance control strategy in multi-input dc/dc converters, which gives control flexibility to the NPC multilevel inverters to effectively track the grid current references. It is greatly different from the voltage-balance control strategies used in multilevel inverters to solve the neutral point imbalance issue.

 

V. EXPERIMENTAL VERIFICATION

To verify the correctness and feasibility of the proposed DITLB converter, a small power prototype based on Dspace1006 has been built with the experimental parameters given in Table II. In addition, the drive circuits are designed based on a photocoupler HCPL-3120. For the sake of simplicity, the two input voltages are set to have the same voltage range 48V-80V. To get the output voltage 400V, the referenced capacitor voltages UC2* and UC3* are both set to 200V. Both steady state and dynamic experimental results have been given. In addition, an efficiency analysis for the proposed DITLB converter under both the ISP and SSP modes is presented.

TABLE IIEXPERIMENTAL PARAMETERS

A. Steady State Experiments

According to the analysis in Section III, the converter under the ISP mode with different input sources operate at the same main circuit. Thus, experimental results of the converter, when Uin1 with 48V supplies energy to the load independently, are given in Fig. 9. In addition, experimental results, when Uin2 with 80V feeds the load independently, are presented in Fig. 10.

Fig. 9.Under ISP mode with Uin1 48V.

Fig.10.Under ISP mode with Uin2 80V.

As can be seen from Fig. 9 and Fig. 10, the output voltage is stable with 400V no matter which input source is used. The duty cycles of S1 and S2 decrease when the input voltage changes from 48V to 80V. The inductor current ripple and input current ripples are given to compare with their theoretical values, as shown in Table III. The theoretical values are calculated based on (10), (11) and the tested duty cycle D. In TABLE III, ΔiL* means the theoretical value of the two same inductor current ripples, and Δiin1* means the theoretical value of the input current ripple. The experimental values are in good agreement with theoretical values. In addition, the input current ripple is small due to the interleaved scheme. More importantly, the ripple frequency of the input current 50kHz is two times the switching frequency 25kHz, which helps design an input filter with a smaller size.

TABLE IIICOMPARATIVE ANALYSIS

Under the SSP mode, key experimental waveforms with different input voltages are presented in Fig. 11 and Fig. 12. With two different input voltages, the converter can still operate with a stable output voltage 400V. In addition, the capacitor voltages are all 200V, which is half of the output voltage. According to (24) and (25), the theoretical values for IL1 and IL2 when Uin1 is 48V and Uin2 is 80V, are 3.33A and 2.00A, respectively. In addition, in the experiment test, IL1 is 3.68A and IL2 is 2.10A, which basically agrees with the theoretical values. Furthermore, when Uin1 is 80V and Uin2 is 48V, IL1 is 2.12A and IL2 is 3.66A, which also agrees with the theoretical values of 2.10A and 3.68A.

Fig. 11.Under SSP mode with Uin1 48V and Uin2 80V.

Fig.12.Under SSP mode with Uin1 80V and Uin2 48V.

Terminal voltage waveforms of S1, S2, D1, D2, and D3 under the ISP mode when Uin1 is 48V are taken as an example to be presented in Fig. 13. It should be noted that uS1 and uS2 are defined to describe the voltage difference between the collector terminal and the emitter terminal of the IGBTs S1 and S2. In addition, uD1, uD2, and uD3 are given to define the voltage difference between the cathode and the anode of the power diodes D1, D2, and D3. It is clear from Fig. 13 that the top voltages of all of the switches and diodes in the converter are 200V, which is half of the output voltage 400V. In addition, it is not difficult to know that the conduction and shutdown of D1 is complementary to that of D2, and that the conduction and shutdown of D1 has a phase shift of 180 degrees with D3. Furthermore, the conduction and shutdown of S1 also has a phase shift of 180 degrees with S2. All these results verify correctness and feasibility of the proposed converter.

Fig. 13.Under ISP mode with Uin1 48V.

B. Dynamic Experiments

Dynamic researches on the proposed DITLB converter have also been carried out. Dynamic experimental waveforms of the DITLB under the ISP mode with different jump conditions are presented in Fig. 14. Dynamic results of the DITLB under the SSP mode when Uin1 jumps from 48V to 70V and Uin2 jumps from 48V to 80V simultaneously, are presented in Fig. 15.

Fig.14.Dynamic experimental waveforms under ISP mode.

Fig.15.Dynamic experimental waveforms under SSP mode: Uin1 jumps from 48V to 70V and Uin2 jumps from 48V to 80V.

As shown in Fig. 14(a), when Uin1 with 48V jumps to Uin2 with 80V, IL2 drops from 3.68A to 2.10A and Iin drops from 7.40A to 4.24A. In addition, Uo increases and then drops to be stable with 400V. In Fig. 14(b), when Uin1 with 80V jumps to Uin2 with 48V, IL2 increases from 2.12A to 3.66 and Iin increases from 4.21A to 7.39A. In addition, Uo drops a little and then increases to be stable with 400V. The dynamic process in Fig. 14 is quick with about a 0.3 second response time under the two jump conditions. Under the SSP mode as shown in Fig.15, the two inductor currents become stable again after about a 0.2 second response time. During this period, the two output capacitor voltages do not change greatly.

Additionally, the dynamic voltage-balance process between C1 and C2 when the converter operates under the ISP mode when Uin1 with 48V, is presented in Fig.16, in which the voltage-balance loop shown in Fig.6 is first not added and then added, and finally removed. It can be seen from Fig.16 that when the voltage-balance loop is not added, there is about a 5V voltage difference between UC1 and UC2, where UC1 is 195V and UC2 is 200V. In addition, d1 is equal to d2 with the value 0.788. However, when the voltage-balance loop is added, UC1 and UC2 are both balanced with the same voltage 200V. In addition, d1 is 0.797 and d2 is 0.789 with a very small duty-cycle difference 0.008, which strongly supports (26). Furthermore, steady state and dynamic experimental results verify that the voltage-balance loop does not affect the voltage-current loop of the converter.

Fig.16.Dynamic voltage-balance process between C1 and C2 under ISP mode with Uin1 48V.

C. Efficiency Analysis

In the end, the conversion efficiency curve versus the input voltage for the DITLB converter under both the ISP mode and the SSP mode with different input voltages are presented in Fig. 17. For the ISP mode, the conversion efficiency curve is presented with the black line in Fig. 17 when input source 2 increases by 4V. For the SSP mode, the conversion efficiency curve is plotted with the blue line when the two input sources increase by 4V. Under the ISP mode, the maximum efficiency is 94.4% and the minimum efficiency is 90.1%. In addition, under the SSP mode, the maximum efficiency is 95.0% and the minimum efficiency is 90.2%. It can be concluded that as the input voltage increases, the conversion efficiency increases a little. When input voltage increases with a stable output voltage and a stable output power, the input current decreases. This reduces the conduction losses of the IGBTs and the power diodes.

Fig. 17.Efficiency curves under ISP and SSP modes.

Based on all of the experimental results, the operating principle analysis and the performance analysis for the proposed converter are correct and the closed-loop control strategy together with the voltage-balance control loop are feasible.

 

VI. CONCLUSION

This paper introduces a new interleaved DITLB converter, which can operate under both the ISP and SSP modes. The input current ripple is small since the converter can operate with an interleaved control scheme. The output capacitor voltages can be easily balanced by a simple voltage-balance control loop under the ISP mode. Under the SSP mode, the two output capacitor voltages are controlled to be equal since they are independently controlled by two voltage-current loops with the same referring capacitor voltage. Experimental results verify the effectiveness and feasibility of the proposed DITLB converter.