A Digital Self-Sustained Phase Shift Modulation Control Strategy for Full-Bridge LLC Resonant Converters

Abstract

A digital self-sustained phase shift modulation (DSSPSM) strategy that allows for good soft switching and dynamic response performance in the presence of step variations is presented in this paper. The working principle, soft switching characteristics, and voltage gain formulae of a LLC converter with DSSPSM have been provided separately. Furthermore, the method for realizing DSSPSM is proposed. Specifically, some key components of the proposed DSSPSM are carefully investigated, including a parameter variation analysis, the start-up process, and the zero-crossing capture of the resonant current. The simulation and experiment results verify the feasibility of the proposed control method. It is observed that the zero voltage switching of the switches and the zero current switching of the rectifier diodes can be easily realized in presence of step load variations.

I. INTRODUCTION

The traveling-wave tube (TWT) microwave transmitter has a wide bandwidth and a high gain, and it can be used for various applications, including communications, radar, electronic countermeasures, and space applications. The power converter is one of the key modules of the microwave transmitter, which is used to power the TWT. With the development of modern microwave systems, some parameter criterions of TWT power converters are gradually increasing, including the efficiency, power density, and dynamic response [1]-[3]. Resonant converter topologies are usually adopted to meet the high efficiency requirements of the TWT power converter, such as the parallel resonant converter, LCC resonant converter, and full-bridge phase-shift converter [4], [5]. Moreover, the LLC resonant converter has been attracting more and more attention due to its inherent merits, including high efficiency, high power density, soft switching, and low EMI [6]-[10]. Therefore, the LLC converter is a preferred candidate for microwave transmitters.

The TWT is a special load for a power converter. The TWT load is prone to sudden and repeated changes with the pulse modulation of pulsed microwave transmitters. Considering these step load variations, the power converter should possess good dynamic response and soft switching characteristics. At present, the power converter has not been widely studied in the context of such step load variations, especially with respect to transient soft switching. To overcome these drawbacks, the converter topology should be improved, and a novel applicable control strategy should be developed [11]-[14].

Self-sustained phase shift modulation (SSPSM) has been proposed for resonant converters in [15] and [16]. This control scheme is inspired by a timing signal from the resonant current. In this manner, the control system is insensitive to parameter uncertainties, and the gate pulses of the switches can be changed adaptively according to the operating conditions. Unlike the conventional frequency modulation (FM) control, SSPSM has much smaller frequency variation range [15], which makes it easy to optimize the magnetic components and to realize miniaturization. Unlike the conventional phase shift modulation (PSM) control, SSPSM can improve soft switching in a wide operation range, which can achieve a higher efficiency [15].

There has been considerable research on SSPSM [16]-[18]. The working principle and design method of a full-bridge LCC converter under SSPSM have been presented in [15]-[17]. The sliding-mode control of a full-bridge LCC converter under SSPSM has been introduced in [18]. These references mainly concentrate on the basic working principles of full-bridge LCC converters under SSPSM, in which the characteristics of SSPSM associated with the parameter variations have not been widely analyzed. In addition, in these references, the SSPSM is realized by analog circuits, which are quite complicated, and some of their control functions are difficult to implement. For example, the loop for adaptively compensating the sawtooth wave is difficult to achieve. Consequently, digital self-sustained phase shift modulation (DSSPSM) used for other novel converter topologies in the presence of parameter variations needs to be investigated further.

The major contribution of this paper is the design and development of a novel DSSPSM control strategy. Some new technical factors of DSSPSM, which are used for LLC converters in the presence of the step load variations have been proposed. First, the working principle of a LLC converter with DSSPSM is discussed, which provides new insights into the improvement of the soft switching and dynamic response characteristics of LLC converters. Second, the parameter design method of DSSPSM is presented, which is used to implement the soft switching. Third, a concrete realization method of DSSPSM is elaborated, especially in applications associated with parameter variations. Finally, the transient soft switching of the resonant converter is analyzed and evaluated.

The rest of this paper is organized as follows. The full bridge LLC resonant converter is discussed under DSSPSM in Section II. After that, the hardware and software realization of the DSSPSM is presented in Section III. Then, the key parts of the DSSPSM design are elaborated upon in Section IV. Simulation and experimental results are given in Section V. Finally, some concluding remarks are provided in Section VI.

 

II. FULL BRIDGE LLC RESONANT CONVERTER UNDER DSSPSM

A. Circuit Analysis

Fig. 1 shows a schematic of the proposed full-bridge LLC converter with a voltage multiplier rectifier under DSSPSM. The switch pairs Q1 and Q2 as well as Q3 and Q4 form the full-bridge inverter. The resonant inductor Lr, transformer magnetic inductor Lm, and resonant capacitor Cr form the LLC resonant tank. The diodes D5 and D6, and the capacitors C5 and C6 form the symmetrical multiplier rectifier. The DSSPSM and proportional plus integral (PI) control are adopted to implement the feedback control.

Fig. 1.Schematic of the proposed full-bridge LLC converter.

The main features of the proposed converter can be summarized as follows.

1) Because the phase-shifting angle is the main control variable to regulate converters under DSSPSM, the switching frequency of a converter with DSSPSM has minimalistic variance, which can optimize the magnetic components and passive filters with respect to the volume and losses [15].

2) The timing signal of DSSPSM is derived from the resonant current, which can form a control loop. In this way, the control scheme can eliminate the sensitivity to parameter variations, and the control system can compensate for variations.

3) The control scheme can ensure that the resonant current iLr lags behind the inverter output voltage vab under any operating condition to realize zero voltage switching (ZVS) of the switches by adjusting the shifting-phase angle, which results in increased efficiency and improved reliability. In addition, zero current switching (ZCS) of the rectifier diodes can be easy to realize under DSSPSM.

4) A symmetrical voltage multiplier rectifier is proposed, which benefits the realization of a high-voltage output and miniaturization of power converters.

B. Working Principle

Fig. 2 shows the working principle of the proposed DSSPSM. γa is the phase angle between the reverse resonant current –iLr and drain-source voltage vao of Q2, and γb is the phase angle between the resonant current iLr and drain-source voltage vbo of Q4. The sawtooth wave vst is a modulation wave, whose amplitude should be almost constant. vca and vcb are two modulation lines; vca is the upper modulation line, vcb is the lower modulation line, and vca ≥ vcb. If the gradient k of vst is assumed to be constant, vca and vcb can be described by the following functions, vca = kγa and vcb = kγb. Usually, vca is kept constant, and vcb is used as the control variable to regulate the converter.

Fig. 2.Working principle of DSSPSM.

Fig. 3 shows typical waveforms of a LLC converter under DSSPSM. In terms of the timing diagrams, there are ten switching modes in a complete switching cycle, and the resonance mode between two components (Lr and Cr) and the resonance mode between three components (Lr, Lm and Cr) are involved. iLr is the resonant current, and iLm is the magnetizing current. When iLr > iLm, the two component resonance occurs. When iLr = iLm, the three component resonance occurs. The starting moment of the two component resonance (the stopping moment of the three component resonance) corresponds to the time when the switches are turned on or off, such as the times t0 and t2. The stopping moment of the two component resonance (the starting moment of the three component resonance) is not related to the time that the switches are turned on and off, such as the times t1 and t3. The energy of the resonant tank is sent to the load by the form (iLr – iLm).

Fig. 3.Typical waveforms of LLC converter under DSSPSM.

C. Soft-Switching Analysis

1) ZVS Analysis of the Switches: In order to realize ZVS of the switches, according to Fig. 2, the polarity of the resonant current iLr should be kept in the dead time Td between Q1 & Q2 or Q3 & Q4, and the limited condition is given by:

The function can be further expressed as:

where, fs is the switching frequency, and Vp is the amplitude of the sawtooth wave vst.

Function (2) can be realized by selecting suitable parameters. In this situation, the resonant current iLr lags behind the inverter output voltage vab, and the zero crossing points of the resonant current are within the inverter output voltage pulse vab. When one switch is turned on, the resonant current flows through the antiparallel body diode of this switch, and then its drain-source voltage is clamped to zero. In this case, ZVS can be implemented.

2) ZCS Analysis of the Rectifier Diodes: Under DSSPSM, if γa – γb > 0, the period where vab = 0 is certain to exit in one switch cycle. In Fig. 2, Tz represents the period where vab = 0. At the beginning of vab = 0 (such as the moment tc in Fig. 2), if iLr = iLm, the converter enters into the three component resonance. If iLr > iLm, the load power is supplied by the LC (Lr and Cr) resonant tank, the resonant current iLr decreases fast, and soon iLr = iLm. Tr represents this decreasing period. If Tz > Tr, the converter will enter into the three-component resonance.

In order to realize ZCS of the rectifier diodes, the three component resonance should always exist in one switch cycle, and the limited condition is given by:

The function can be further expressed as:

Function (4) can be realized by selecting suitable parameters. In this situation, all of the rectifier diodes are switched off with zero current. This reduces the reverse recovery losses of the diodes, which contributes to increased efficiency.

D. Modeling Analysis

In order to guide the circuit analysis and parameter design, based on the First Harmonic Approximation (FHA) method [19], [20], a LLC converter model under DSSPSM is built.

The fundamental component vab1 of the inverter output voltage vab can be expressed as:

The effective value vab1 of vab1 is described as:

The symmetrical multiplier rectifier can be simplified as Fig. 4(a). The fundamental component vs1 of the inverter voltage vs can be expressed as:

The RMS value (Vs1) of vs1 is described as:

The fundamental component is1 of the inverter current is can be expressed as:

The equivalent reflected impedance Req of the multiplier rectifier can be derived as:

Through the above analysis, the equivalent circuit of the LLC converter can be shown as Fig. 4(b).

Fig. 4.Equivalent circuit of the LLC converter. (a) Symmetrical multiplier rectifier. (b) Equivalent circuit of the LLC converter.

The equivalent reflected impedance Rac on the primary side of the transformer can be expressed as:

The open loop transfer function of the LLC resonant tank can be given as:

Considering (6), (8), and (12), the DC gain of the resonant tank can be obtained as:

The DC gain of the LLC converter can be expressed as:

where:

According to (15), the voltage gain curves of a full-bridge LLC converter with DSSPSM are plotted, as shown in Fig. 5. According to this figure, the voltage gain M increases with respect to the increase in phase γb. By controlling the phase γb, vcb is controlled, and the converter can be regulated. In addition, when the frequency ratio F decreases, the phase γb varies little with the same gain change, and the gain range becomes wide, as shown in Fig. 5(a). When the quality factor Q increases, the voltage gain M becomes small, as shown in Fig. 5(b).

Fig. 5.Voltage gain curves versus γb. (a) Q =0.3, γa=0.9π, n=1, k=4. (b) F=0.9, γa=0.9π, n=1, k=4).

 

III. REALIZATION OF DSSPSM

A. Hardware Realization

Fig. 6 shows a hardware realization schematic of DSSPSM. Fig. 7 illustrates the main waveforms of DSSPSM based on a DSP. A DSP board by Texas Instruments (TMS320F2812) is primarily used to implement the control scheme. The general timer of the DSP event manager is set to the continuous incremental mode, and is used to generate the sawtooth wave vst. The comparison unit registers CMPR1 and CMPR2 separately represent the modulation lines vca and vcb. The logic signals vr1 and vr2 are separately obtained by comparing vst with vca and vcb. The zero-crossing moment of the resonant current can be captured by the DSP, and then the signal vr3 can be easily generated.

Fig. 6.Hardware schematic of DSSPSM.

Fig. 7.Main waveforms of DSSPSM based on DSP.

In Fig. 6, the logic signals vr1, vr2, and vr3 can be converted to the drive signals LQ1–LQ4, through the logic operations of NOT gate, NAND gate, and RS flip-flop. After that, the dead-time of LQ1-LQ4 is generated by the RCD circuit. Lastly, two drive chips Si8235 are used to drive the switches.

B. Software Realization

Fig. 8 shows software realization flowcharts of DSSPSM. The software is mainly composed of the main program and the interrupt programs, and the interrupt programs consist of the capture interrupt, the timer-underflow interrupt, and the analog-to-digital conversion (ADC) interrupt.

Fig. 8.Software flowcharts of DSSPSM. (a) Main program. (b) Capture interrupt program. (c) ADC interrupt program.

Fig. 8(a) shows the main program flowchart. The program initialization is carried out first, and then the main program waits to respond to the interrupt flags.

Fig. 8(b) shows a capture interrupt program flowchart. The capture interrupt is stimulated at the zero-crossing moment of the resonant current. The zero-crossing moment can be captured, and the zero-crossing period can be calculated. If the captured period belongs to the predetermined scope, the timer counter returns to zero. If the captured period does not belong to the predetermined scope, the timer period register is updated.

The program flowchart of the timer underflow interrupt is relatively simple. The timer underflow interrupt is stimulated when the timer counter becomes zero. The zero-crossing square wave vr3 is generated in this program, and then the ADC converter is stimulated by the timer underflow interrupt flag.

Fig. 8(c) shows an ADC interrupt program flowchart. The ADC interrupt is stimulated by the ADC flag. After the sampled value is obtained, the feedback control signal can be calculated by the digital position PI control algorithm, and then the comparison register CMPR2 is updated by the feedback control value.

 

IV. KEY PARTS OF DSSPSM DESIGN

A. DSSPSM Design Regarding Parameter Variations

Parameter variations of the converter, such as step load variations, introduce some problems to the DSSPSM design. For instance, the sawtooth wave may have distortions. Fig. 9 shows simulation results of the sawtooth wave when the load is changed repeatedly between 600 Ω and 1200 Ω every 2.5 ms. It can be seen that the amplitude of the sawtooth wave begins to change at the load change moment. This phenomenon may lead to some mistakes, and some measures should be taken.

Fig. 9.Simulation results of sawtooth wave changes with respect to step load variations.

Fig. 10 shows two concrete mistakes associated with the sawtooth wave of DSSPSM.

Fig. 10.Concrete mistakes of sawtooth wave of DSSPSM ((a) The first mistake and (b) The second mistake).

As shown in Fig. 10(a), during the period T1(k+1), for the zero-crossing moment of the resonant current advances, the captured zero-crossing period T1(k+1) is less than the normal value T1(k), and the amplitude Vp1 of the sawtooth wave is less than the normal amplitude TPR of the sawtooth wave vst in the period T1(k+1). In this situation, if the modulation line vca is larger than the amplitude Vp1, the logic signal vr1 cannot be obtained in the correct manner. As a result, the gate pulses of the switches will be wrong.

As shown in Fig. 10(b), during the period T2(k+1), for the zero-crossing moment of the resonant current delays, the captured zero-crossing period T2(k+1) is larger than the normal value T2(k), and two sawtooth waves will appear in the period T2(k+1). In this situation, the logic signal vr3 will be wrong. In addition, if the amplitude Vp2 of the second sawtooth wave in the period T2(k+1) is larger than the modulation line vcb, the logic signal vr2 can not be obtained in the correct manner. As a result, the gate pulses of the switches will be wrong.

In order to fix the two mistakes shown in Fig. 10, some measures should be taken.

1) For the mistake shown in Fig. 10(a), the parameter variations should be taken into consideration when selecting the value of vca. The value of vca should be always less than the normal amplitude TPR of the sawtooth wave vst. Moreover, if the captured amplitude Vp1 is less than vca, the value of vca should be immediately updated as:

2) For the mistake shown in Fig. 10(b), if the captured zero-crossing period T2(k+1) is larger than the normal value T2(k), the value of TPR should be immediately updated as:

B. Start-Up Process

There are several situations that warrant consideration in the start-up process.

1) The resonant current may not be regular and stable in the start-up process, and DSSPSM may become unreliable.

2) A sudden power-on may impact the converter hardware, so soft starting should be realized.

In order to solve these two problems, following measures should be taken.

1) In the start-up period, the traditional phase shift control is adopted first. When the converter becomes stable, the DSSPSM control begins to work.

2) The control signal vcb varies slowly from zero to a predetermined value, and the pulse width of the inverter output voltage vab becomes gradually wider. In this way, soft starting can be realized.

C. Zero-Crossing Capture

Zero-crossing capture is a vital part of the DSSPSM design. If the zero-crossing moment cannot be correctly captured, DSSPSM may not work. Fig. 11 shows the zero-crossing detection circuit. A hall-effect current sensor TBC06DS3.3 is adopted to sample the resonant current, and the zero-crossing square-wave of the resonant current is obtained through an ultrafast comparator LT1720. However, the rising edge and falling edge of the square-wave may have some chattering. Therefore, the figuration function of this square-wave needs to be achieved through a RC filter and NOT gate 74LS14. In this way, the zero-crossing signal can be obtained in a correct manner, and sent to the capture port of the DSP.

Fig. 11.Zero-crossing detection circuit.

 

V. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results

In order to evaluate the performance of the proposed DSSPSM control strategy, some simulation results are presented in this section. The simulations are carried out with MATLAB/SIMULINK software.

The simulation and experiment are carried out on a LLC resonant converter with an input voltage of 270 V. The resonant frequency is set to 115 kHz with a Lr of 104 μH and a Cr of 20 nF. The magnetic inductor Lm is set to 416 μH. Thus, Lr/Lm is 4. The main parameters of the designed converter are shown in Table I.

Table ICONVERTER PARAMETERS

Fig. 12 shows typical simulation waveforms of DSSPSM, including the resonant current iLr, the sawtooth wave vst, the drain-source voltage vao of the switch Q2, the drain-source voltage vbo of the switch Q4, and the inverter output voltage vab. As can be seen, the simulation results are in accordance with the theoretical analysis.

Fig. 12.Typical simulation waveforms of DSSPSM.

Fig. 13 shows a simulation waveform of the output voltage vo with respect to step load variations. The load resistance is changed between 600 Ω and 1200 Ω every 2.5 ms. As can be seen, the output voltage vo has a little ripple against the step load changes, and the converter stays stable during the entire process.

Fig. 13.Simulation waveform of output voltage vo with respect to step load variations.

Fig. 14 shows simulation waveforms of the resonant current iLr and inverter output voltage vab in the presence of step load variations. As can be seen, iLr is kept lagging behind vab when the load resistance becomes larger or smaller. In this situation, when one switch is turned on, the resonant current flows through the antiparallel body diode and the drain-source voltage is clamped to zero. Then the ZVS can be realized.

Fig. 14.Simulation waveforms of resonant current iLr and inverter output voltage vab with respect to step load variations ((a) From 600 Ω to 1200 Ω and (b) From 1200 Ω to 600 Ω).

B. Experimental Results

In order to investigate the performance of the proposed DSSPSM control strategy, a laboratory prototype has been built, as shown in Fig. 15. The parameters of the converter are listed in Table I.

Fig. 15.Laboratory prototype.

1) Steady State Performance: Fig. 16 shows experimental waveforms of the resonant current iLr and zero-crossing square signal vr3 at a full load. As can be observed, there is no chattering in the rising edge or falling edge of vr3, and the zero-crossing moment can be correctly captured by the DSP.

Fig. 16Experimental waveforms of resonant current iLr and zero-crossing square wave vr3.

Fig. 17 shows experimental waveforms of the resonant current iLr and inverter output voltage vab at a full load, half load and light load (10% load). As can be seen, under different load conditions, iLr can lag behind vab, and all of the switches can implement ZVS which reduces the switching losses of the switches.

Fig. 17.Experimental waveforms of resonant current iLr and inverter output voltage vab ((a) Full load, (b) Half load and (c) Light load (10% load)).

Fig. 18 shows experimental current waveforms of the rectifier diodes D5 and D6 at a full load, half load, and light load (10% load). All of the rectifier diodes can implement ZCS which reduces the reverse recovery losses of the rectifier diodes.

Fig. 18.Experimental current waveforms of the rectifier diodes D5 and D6 ((a) Full load, (b) Half load and (c) Light load (10% load)).

2) Dynamic State Performance: Fig. 19 shows transient waveforms of the reverse resonant current -iLr and inverter output voltage vab under the conventional PSM in the presence of of step load variations. As can be seen, the current iLr cannot keep lagging behind the voltage vab, and sometimes the soft switching characteristic of the converter is not so good for the step load variations.

Fig. 19.Transient waveforms under PSM for the step load variations.

Fig. 20 shows transient waveforms of the resonant current iLr, inverter output voltage vab and output voltage vo under DSSPSM in the presence of step load variations. Fig. 20(a) shows waveforms when the load resistance increases. Fig. 20(b) shows waveforms when the load resistance decreases. The load resistance is changed between 600 Ω and 1200 Ω, and the load changing transition time is less than 200 ns.

Fig. 20.Transient waveforms under DSSPSM for the step load variations ((a) From 600 Ω to 1200 Ω and (b) From 1200 Ω to 600 Ω).

As can be seen, iLr is kept lagging behind vab for step load variations, and ZVS can always be implemented. In addition, the converter has good dynamic performance, and the output voltage vo can be tightly regulated at 550 V. The response time is less than 150 μs, and the output voltage overshoot and undershoot are less than 1% of 550 V.

3) Efficiency Analysis: Fig. 21 shows an efficiency curve according to the load. The figure indicates that the efficiencies under different load conditions are higher than 92%, and their variance is minimalistic. The soft switching of the LLC converter with DSSPSM can be realized under different load conditions leading to an improved efficiency in a wide operation range.

Fig. 21.Efficiency curve according to load.

 

VI. CONCLUSION

In this paper, a novel DSSPSM control strategy is proposed, and a full bridge LLC resonant converter with a multiplier rectifier under DSSPSM is introduced. The working principle, soft-switching characteristic, and realization procedure of DSSPSM are separately analyzed. Simulation and experimental results validate that the proposed LLC converter under DSSPSM has a good dynamic performance and soft switching characteristics in presence of the step load variations. Therefore, the proposed DSSPSM control strategy is valuable for improving the efficiency and power density of power converters. In addition, a simulated resistance load is used to represent a TWT in the simulation and experiment, which makes it easy to test the steady-state and dynamic-state performance of DSSPSM. In future work, the practical application of DSSPSM in TWT microwave transmitters will be explored.