한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제41권11호
  • /
  • Pages.1502-1506
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  • 2016
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  • 1226-4717(pISSN)
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  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
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HEVC 용 고속 인트라 예측 VLSI 구현

High-Speed Intra Prediction VLSI Implementation for HEVC

  • Jo, Hyeonsu (Dongguk University Department of Electronic & Electrical Engineering) ;
  • Hong, Youpyo (Dongguk University Department of Electronic & Electrical Engineering) ;
  • Jang, Hanbeyoul (Dongguk University Department of Electronic & Electrical Engineering)
  • 투고 : 2016.08.31
  • 심사 : 2016.10.10
  • 발행 : 2016.11.30
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⟨ 이전 논문 다음 논문 ⟩

초록

HEVC (High Efficiency Video Coding)는 최근에 제안된 비디오 압축 표준으로서 이전의 비디오 압축 표준보다 두 배 이상의 부호화 효율을 가진다. 다양한 종류의 인트라 예측 블록과 모드는 HEVC의 높은 압축 성능과 연산 복잡도 증가의 주요 요인이다. 본 논문은 파이프라인과 인터리빙 기술을 사용하여 하드웨어 자원의 요구조건을 줄이는 반면 효율과 성능은 향상시킨 HEVC 용 인트라 예측 하드웨어 구조를 제시한다.

HEVC (High Efficiency Video Coding) is a recently proposed video compression standard that has a two times greater coding efficiency than previous video compression standards. The key factors of high compression performance and increasement of computational complexity are the various types of block partitions and modes of intra prediction in HEVC. This paper presents an intra prediction hardware architecture for HEVC utilizing pipelining and interleaving techniques to increase the efficiency and performance while reducing the requirement for hardware resources.

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참고문헌

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