Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of the Multiplier in case of P=2 over the Finite Fields based on the Polynomial

다항식에 기초한 유한체상의 P=2인 경우의 곱셈기 설계

  • Park, Chun-Myoung (Department of Computer Engineering, Korea National University of Transportation)
  • 박춘명 (한국교통대학교 컴퓨터공학과)
  • Received : 2015.12.16
  • Accepted : 2016.01.22
  • Published : 2016.02.25
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Abstract

This paper proposes the constructing method of effective multiplier based on the finite fields in case of P=2. The proposed multiplier is constructed by polynomial arithmetic part, mod F(${\alpha}$) part and modular arithmetic part. Also, each arithmetic parts can extend according to m because of it have modular structure, and it is adopted VLSI because of use AND gate and XOR gate only. The proposed multiplier is more compact, regularity, normalization and extensibility compare with earlier multiplier. Also, it is able to apply several fields in recent hot issue IoT configuration.

본 논문에서는 다항식에 기초하여 유한체상의 P=2인 경우의 효율적인 곱셈기를 구성하는 방법을 제안하였다. 제안한 곱셈기 회로는 다항식의 연산부와 mod F(${\alpha}$) 연산부, 모듈러 연산부로 구성된다. 또한, 이들 각 연산부는 모듈 구조를 가지므로 m의 확장에 따른 회로 구성이 용이하며 회로 구성에 사용한 소자는 AND 게이트와 XOR 게이트만으로 구성하여 정규성, 확장성이 용이하며 이를 기반으로 VLSI화에 적합하다. 제안한 곱셈기는 기존의 곱셈기에 비해 좀 더 콤펙트, 규칙적, 정규성과 확장성이 용이하며 최근의 IoT 환경에서의 여러 분야에 적용 및 응용이 가능할 것이다.

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References

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