JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Adaptive Memory Controller for High-performance Multi-channel Memory

  • Kim, Jin-ku (Dept. of Computer Science and Engineering, Sogang University) ;
  • Lim, Jong-bum (Dept. of Computer Science and Engineering, Sogang University) ;
  • Cho, Woo-cheol (Dept. of Computer Science and Engineering, Sogang University) ;
  • Shin, Kwang-Sik (Dept. of Computer Science and Engineering, Sogang University) ;
  • Kim, Hoshik (Dept. of Computer Science and Engineering, Sogang University) ;
  • Lee, Hyuk-Jun (Dept. of Computer Science and Engineering, Sogang University)
  • Received : 2016.04.11
  • Accepted : 2016.08.02
  • Published : 2016.12.30
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Abstract

As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

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References

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