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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Mutual Information Analysis for Three-Phase Dynamic Current Mode Logic against Side-Channel Attack

  • Kim, Hyunmin (Center for Information Security Technologies, Korea University) ;
  • Han, Dong-Guk (Department of Mathematics, Kookmin University) ;
  • Hong, Seokhie (Center for Information Security Technologies, Korea University)
  • Received : 2014.03.10
  • Accepted : 2015.01.28
  • Published : 2015.05.01
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Abstract

To date, many different kinds of logic styles for hardware countermeasures have been developed; for example, SABL, TDPL, and DyCML. Current mode-based logic styles are useful as they consume less power compared to voltage mode-based logic styles such as SABL and TDPL. Although we developed TPDyCML in 2012 and presented it at the WISA 2012 conference, we have further optimized it in this paper using a binary decision diagram algorithm and confirmed its properties through a practical implementation of the AES S-box. In this paper, we will explain the outcome of HSPICE simulations, which included correlation power attacks, on AES S-boxes configured using a compact NMOS tree constructed from either SABL, CMOS, TDPL, DyCML, or TPDyCML. In addition, to compare the performance of each logic style in greater detail, we will carry out a mutual information analysis (MIA). Our results confirm that our logic style has good properties as a hardware countermeasure and 15% less information leakage than those secure logic styles used in our MIA.

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References

  1. P. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Annual Int. Cryptography Conf., Santa Barbara, CA, USA, Aug. 15-19, 1999, pp. 388-397.
  2. M. Bucci et al., "Three-Phase Dual-Rail Pre-Charge Logic," Workshop Cryptographic Hardware Embedded Syst., Yokohama, Japan, Oct. 10-13, 2006, pp. 232-241.
  3. K. Tiri, M. Akmal, and I. Verbauwhede, "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards," European Solid-State Circuits Conf., Florence, Italy, Sept. 24-26, 2002, pp. 403-406.
  4. F. Mace et al., "A Dynamic Current Mode Logic to Counteract Power Analysis Attacks," Conf. Des. Circuits Integr. Syst., Bordeaux, France, Nov. 24-26, 2004, pp. 186-191.
  5. F. Regazzoni et al., "Evaluation Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology," in Trans. Comput. Sci., Berlin Heidelberg: Springer, 2009, pp. 230-243.
  6. M.W. Allam and M.I. Elmasry, "Dynamic Current Mode Logic (DyCML): A New Low-Power High Performance Logic Style," IEEE J. Solid-State Circuits, vol. 36, no. 3, Mar. 2001, pp. 550-558. https://doi.org/10.1109/4.910495
  7. T. Sundstrom and A. Alvandpour, "A Comparative Analysis of Logic Styles for Secure IC's Against DPA Attacks," Nordic Microelectron. Conf., Oulu, Finland, Nov. 21-22, 2005, pp. 297-300.
  8. M. Renauld et al., "Information Theoretic and Security Analysis of a 65-nanometer DDSLL AES S-Box," Workshop Cryptographic Hardware Embedded Syst. Conf., Nara, Japan, Sept. 28-Oct. 1, 2011, pp. 223-239.
  9. D. Kamel et al., "Analysis of Dynamic Differential Swing Limited Logic for Low-Power Secure Applications," J. Low Power Electron. Appl., vol. 2, no. 1, Mar. 2012, pp. 98-126. https://doi.org/10.3390/jlpea2010098
  10. K. Tiri and I. Verbauwhede, "Design Method for Constant Power Consumption of Differential Logic Circuits," Des. Autom. Test Europe Conf., Munich, Germany, Mar. 7-11, 2005, pp. 628-633.
  11. K. Tiri and I. Verbauwhede, "Place and Route for Secure Standard Cell Design," Smart Card Res. Adv. Appl., Toulouse, France, Aug. 22-27, 2004, pp. 143-158.
  12. L. Lin and W. Burleson, "Analysis and Mitigation of Process Variation Impacts on Power-Attack Tolerance," Des. Autom. Conf., San Francisco, CA, USA, July 26-31, 2009, pp. 238-243.
  13. H. Kim, V. Rozic, and I. Verbauwhede, "Three-Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption," Int. Workshop Inf. Security Appl., Jeju, Rep. of Korea, Aug. 16-18, 2012, pp. 68-81.
  14. S.B. Akers, "Binary Decision Diagrams," IEEE Trans. Comput., vol. C-27, no. 6, June 1978, pp. 509-516. https://doi.org/10.1109/TC.1978.1675141
  15. E. Brier, C. Clavier, and F. Olivier, "Correlation Power Analysis with a Leakage Model," Workshop Cryptographic Hardware Embedded Syst., Cambridge, MA, USA, Aug. 11-13, 2004, pp. 16-29.
  16. F.-X. Standaert, T.G. Malkin, and M. Yung, "A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks," Annual Int. Conf. Theory Appl. Cryptographic Techn., Cologne, Germany, Apr. 26-30, 2009, pp. 443-461.
  17. F. Mace, F.-X. Standaert, and J.-J. Quisquater, "Information Theoretic Evaluation of Side-Channel Resistant Logic Styles," Workshop Cryptographic Hardware Embedded Syst., Vienna, Austria, Sept. 10-13, 2007, pp. 427-442.
  18. N. Mentens et al., "Systematic Evaluation of Compact Hardware Implementation for the Rijdael S-Box," Cryptographers' Track RSA Conf., San Francisco, CA, USA, Feb. 14-18, 2005, pp. 323-333.
  19. X. Zhang and K.K. Parhi, "High-Speed VLSI Architectures for the AES Algorithm," IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 9, Sept. 2004, pp. 957-967. https://doi.org/10.1109/TVLSI.2004.832943
  20. H.R Anderson, An Introduction to Binary Decision Diagrams, The IT University of Copenhagen, Lecture Notes for Efficient Algorithms and Programs, Fall 1999. Accessed Mar. 24, 2015. http://www.cmi.ac.in/-madhavan/courses/verification-2011/andersen-bdd.pdf
  21. J. Cortadella, "Mapping BDDs into DCVSL Gates," UPC/DAC (Universitat Politecnica de Catalunya), Barcelona, Spain, Tech. Rep. No. RR 95/04, Feb. 1995.
  22. F.-X. Standaert, T.G. Malkin, and M. Yung, "A Formal PracticeOriented Model for the Analysis of Side-Channel Attacks," Cryptology ePrint Archive (http://eprint.iacr.org), Rep. 2006/139, 2006.

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