DOI QR코드

DOI QR Code

데이터링크 통신을 위한 PLL 주파수합성기 설계

Design of PLL Frequency Synthrsizer for Data Link Communication

  • 권상철 (에이스안테나 방산 연구소) ;
  • 강경식 (명지대학교 산업경영공학과)
  • 투고 : 2015.07.20
  • 심사 : 2015.09.18
  • 발행 : 2015.09.30

초록

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

키워드

참고문헌

  1. Yun-Soo Ko(1999), "Design and Fabrication of PLL module for WLL" Department of Radio Science & Engineering, Graduate School Chungnam National University.
  2. Joon-Gyu Ryu(2001), "Design and Fabrication of Fractional-N PLL module for IMT-2000", Department of Radio Science & Engineering, Graduate School Chungnam National University.
  3. Choong-Ho Zee(2005), "Design and Fabrication of DDS/PLL Hybrid Wideband Frequency Synthesizer", Department of Radio Science & Engineering, Graduate School Chungnam National University.
  4. Ki-Jeong Lee(2003), "Design and Fabrication of DDS-driven PLL", Department of Radio Science & Engineering, Graduate School Chungnam National University.
  5. Kyung-Soo Ha(2004), "Design and Fabrication of DDS/PLL Hybrid Frequency Synthesizer", Department of Radio Science & Engineering, Graduate School Chungnam National University.
  6. Yong Kim(1999), "The Design and Fabrication of Voltage-Controlled Oscillator in C-Band", Department of Radio Science & Engineering, Graduate School Chungnam National University.
  7. Soo-Seul Hwang(2000), "Design and Fabrication of Dual-Mode PLL module using Switchable VCO", Department of Radio Science & Engineering, Graduate School Chungnam National University.