High Step-Up Converter with Hybrid Structure Based on One Switch

Abstract

A novel high step-up converter is presented herein, which combines the conventional buck-boost converter, the charge pump capacitor and the coupling inductor. By doing so, a quite high voltage conversion ratio due to not only the turns ratio but also the duty cycle, so as to increase design feasibility. It is noted that the denominator of the voltage conversion ratio is the square of one minus duty cycle. Above all, there is no voltage spike across the switch due to the leakage inductance and hence no passive or active snubber is needed, and furthermore, the used switch is driven without isolation and hence the gate driving circuit is relatively simple, thereby upgrading the industrial application capability of this converter. In this paper, the basic operating principles and the associated mathematical deductions are firstly described in detail, and finally some experimental results are provided to demonstrate the effectiveness of the proposed high step-up converter.

1. Introduction

As generally recognized, the boost converter is widely used in the renewable energy system, in the standby power source, in the car power source, in the 3C (Computer, Communication, Consumer-Electronics) product, etc. The purpose of the boost converter is used to transfer the low voltage level to the stable high voltage level, so as to stabilize the overall system. Therefore, the traditional boost converter is used as a power stage, which boosts the input voltage to a 400V dc voltage to feed the standby power source, or to generate a grid-connected 220V ac voltage via the DC-AC inverter. However, the traditional boost converter has the voltage conversion ratio about four. This is because the non-ideal properties due to parasitic components make the voltage conversion ratio deteriorated [1, 2].

Consequently, many kinds of voltage-boosting techniques have been presented, including several inductors which are magnetized and then pump the stored energy into the output with all inductors connected in series [3], coupled inductors with turns ratios [4-8, 9, 10, 14, 18, 19], voltage superposition based on switching capacitors [12-17], auxiliary transformers with turns ratios [11], etc. In [8] and [9], the output terminal is floating, thereby increasing application complexity. In [6, 7] and [10], these converters contain too many components, thereby making the converters relatively complicated. In [3-10, 14-16, 18] and [19], the output currents are pulsating, thus causing the output voltage ripples to tend to be large. In [11-13] and [17], even though the output currents are non-pulsating, their voltage conversion ratios are not high enough.

Therefore, a novel high step-up converter is presented herein, which combines the traditional buck-boost converter, the charge pump and the coupling inductor. This converter possesses relatively high voltage conversion ratio, the designer can use the turns ratio to vary the voltage conversion ratio so as to make the circuit design relatively elastic. Above all, the used power switch is not floating, so as to make the gate driving circuit quite simple. Furthermore, there is no voltage spike across the switch due to the leakage inductance. In this paper, the basic operating principles and the associated mathematical deductions are firstly depicted in detail, and eventually some experimental results are provided to verify the effectiveness of the proposed high step-up converter.

 

2. Overall System Configuration

Fig. 1 shows the proposed high step-up converter, which is constructed by the traditional buck-boost converter, and the coupling inductor and charge pump capacitor circuit. The traditional buck-boost converter contains one switch S1, two diodes D1 and D4, one inductor L1, and one energy-transferring capacitor C1. The coupling inductor and charge pump capacitor circuit contains one switch S1, three diodes D2, D3 and D4, one charge pump capacitor C2, one output capacitor Co, and one coupling inductor with turns ratio of N1:N2, where N1 and N2 are the primary-side turns and the secondary-side turns, respectively. It is noted that the coupling inductor is built up by one magnetizing inductor Lm and one ideal transformer.

Fig. 1.Proposed high step-up converter with variables added.

 

3. Basic Operating Principles

Prior to taking up this section, there are some assumptions and symbols to be given as follows in Fig. 1: (i) the coupling coefficient k is equal to one, that is, the primary and secondary leakage inductances are negligible; (ii) the dc input and output voltages are defined to be Vi and Vo, respectively; (iii) the dc input and output currents are signified by Ii and Io, respectively; (iv) the current in S1 is indicated by iDS1; (v) the currents in D1, D2, D3 and D4 are denoted by iD1, iD2, iD3 and iD4, respectively; (vi) the values of C1 and C2 are large enough to keep the voltages across themselves constant at some values, equal to VC1 and VC2, respectively; (vii) the current flowing through L1 is expressed by iL1; (viii) the currents in the N1 and N2 windings are signified by i1 and i2, respectively; (ix) the current in Lm is indicated by iLm; (x) i3 is the sum of i1 and im; (xi) the gate driving signal for S1 is denoted by vgs1; (xii) the voltages on S1 is represented by vDS1; (xiii) the voltage across L1 is expressed by vL1; (xiv) the voltage across Lm or the voltage across the N1 winding is expressed by vN1; (xv) the voltage on the N2 winding indicated by vN2; (xvi) the turns ratio of n is equal to N2/N1; and (xvii) the duty cycle D is the quiescent dc duty cycle created from the controller.

3.1 CCM Operation

Since the converter operates in the continuous conduction mode (CCM), there are two operating states with the illustrated waveforms as shown in Fig. 2.

Fig. 2.Illustrated waveforms related to the proposed converter.

3.1.1 State 1 (t0 ≤ t ≤ t1)

As shown in Fig. 3(a), S1 is turned on. Hence, the voltage across L1 is equal to Vi, thereby causing L1 to be magnetized. At the same time, D1 and D3 are turned off, but D2 and D4 are turned on. Accordingly, the voltage across Lm, vN1, is equal to the input voltage Vi plus the voltage across C1, VC1, thereby causing Lm to be magnetized. In addition, C2 is charged by Vi+VC1+vN2. Therefore,

Fig. 3.Current flows in: (a) state 1; (b) state 2.

3.1.2 State 2 (t1 ≤ t ≤ t0+Ts )

As shown in Fig. 3(b), S1 is turned off. Hence, D2 and D4 are turned off, but D1 and D3 are turned on. At the same time, the voltage across L1, vL1, is equal to −VC1 , thereby causing L1 to be demagnetized and to energize the output, whereas the voltage across Lm, vN1, is equal to Vi +VC1 +VC2 − vN2 − Vo, thereby causing Lm to be demagnetized. Therefore,

Since the turns ratio n is equal to N2/N1, (2) can be rewritten to be

Applying the voltage-second balance to L1, we can obtain the following equation:

Eq. (4) can be rewritten to be

By applying the voltage-second balance to Lm, we can obtain the following equation:

where

Substituting (5) and (7) into (6) yields the voltage conversion ratio of the proposed high step-up converter:

3.2 Comparison of flyback, forward and proposed converters

As generally acknowledged, the duty cycle of the flyback converter does not approach to one due to the parasitic parameters of components, whereas the duty cycle of the forward converter also does not approach to one due to a suitable time slot needed to reset the magnetizing inductance. Based on the aforementioned, the comparison in voltage conversion ratio between the flyback converter, the forward converter and the proposed converter is under the condition that each converter operates in the continuous conduction mode (CCM) with the turns ratio set to 3 and the duty cycle set at 0.75. Therefore, the voltage conversion ratios for the flyback converter, the forward converter and the proposed converter are 2.25, 9, and 68, respectively. That is, the proposed converter has a quite high voltage conversion ratio as compared with the flyback converter and forward converter.

3.3 CCM with leakage inductance considered

By considering the leakage inductance Llk as shown in Fig. 4, in state 1, the corresponding equation of vN1 expressed by (1) will be modified to

Fig. 4.Proposed high step-up converter with leakage inductance considered.

where k=Lm / (Lm+Llk).

And, in state 2, the corresponding equation of vN1 will be modified to

By applying the voltage balance to the magnetizing inductor based on (9) and (10), the resulting voltage conversion ratio can be obtained to be

From (11), as the value of k is close to one, the voltage conversion ratio is retrieved to (8).

3.3 BCM operation

Since there are two inductors L1 and Lm in the proposed high step-up converter, the corresponding boundary conduction mode (BCM) conditions will be discussed in the following, so as to make design of L1 and Lm relatively easy. It is assumed that there is no power loss, i.e., the input power is equal to the output power.

3.3.1 BCM Condition for L1

Based on (8), the dc input current Ii can be expressed as

where

Substituting (10) into (9) yields

Since the dc current in L1, IL1, is equal to Ii, (11) can be rewritten to be

Also, the current ripple of iL1, denoted by ΔiL1 , can be expressed to be

Hence, the condition for L1 operating in BCM is

where

and

Thus, if K1 is larger than Kcrit1(D), then L1 operates in CCM; if K1 is smaller than Kcrit1(D), then L1 operates in DCM.

3.3.2 BCM Condition for Lm

The dc portion of the current in the magnetizing inductor Lm, denoted by ILm, can be represented by

Substituting (10) into (17) yields

Also, the current ripple of iLm, denoted by ΔiLm , can be expressed to be

Substituting (5) into (19) yields

Hence, the condition for Lm operating in BCM is

Accordingly, K2 is larger than Kcrit2(D), then Lm operates in CCM; if K2 is smaller than Kcrit1(D), then Lm operates in DCM.

 

3. Design Considerations

Prior to taking up this section, there are some system specifications and key components to be given as follows: (i) the range of the dc input voltage Vi is from 20V to 28V with 24V rated; (ii) the rated dc output voltage Vo is 400V; (iii) the rated dc output power Po,rated is 200W, i.e., the rated dc output current Io,rated is 0.5A; (iv) the minimum dc output power Po,min is 40W, i.e., the minimum dc output current Io,min is 0.1A; (v) the switching frequency fs is 50kHz, i.e., the switching period Ts is 20μs; and (vi) the product name of the control IC is MC34060A. It is noted that the proposed converter operates in CCM above the minimum dc output current. In addition, Tables 1 and 2 show the voltage and current stresses of the switch and diodes, and the specifications for the components used in the main power stage of the proposed converter.

Table 1.Voltage and current stresses of the switch and diodes

Table 2.Components used in the main power stage of the proposed converter

Sequentially, the energy-storing components, such as L1, Lm, C1, C2 and Co, are taken into account, under the condition that the converter operates in CCM and the turns ratio of the coupling inductor, n, is set to one.

4.1 Design of L1

Fig. 5(a) shows the waveforms related to L1.In addition, (8) can be rewritten to be

Fig. 5.Waveforms related to: (a) L1; (b) Lm.

From (24), the duty cycle D can be obtained as

Therefore, according to (25), the minimum duty cycle Dmin occurs at the maximum dc input voltage Vi,max, and the maximum duty cycle Dmax occurs at the minimum dc input voltage Vi,min.

Sequentially, based on Fig. 5(a), ΔiL1 can be expressed to be

Therefore, the maximum value of ΔiL1, signified by ΔiL1, max , can be expressed to be

In order to make sure that L1 operates in CCM, the following inequality must be obeyed:

where IL1,min is the minimum dc current in L1.

Also, if the efficiency of the overall system is assumed to be equal to 100%, then the following equation can be obtained to be

Based on (27) to (29), the inequality for L1 can be obtained to be

Therefore, the value of L1 is larger than 115.4μH so as to make sure that L1 operates in CCM. Furthermore, considering the efficiency performance, the higher the value of L1 is, the smaller the peak current in L1 and hence the lower the conduction loss and core loss. Eventually, the value of L1 is chosen to be 225μH, which is about double the calculated value. Also, the core, named CC4220/JPP44A, is selected to construct L1 along with the corresponding turns of 38 and the required air-gap of 1.622mm.

4.2 Design of Lm

Fig. 5(b) shows the waveforms related to Lm. In addition, ΔiLm can be expressed as

According to (5) and (31) can be rewritten as

Therefore, it can be seen that the maximum value of ΔiLm , signified by ΔiLm,max , can be expressed to be

In order to make sure that Lm operates in CCM, the following equation must be obeyed:

where ILm,min is the minimum dc current in Lm and can be expressed to be

Based on (33) to (35), the inequality for Lm can be obtained as

Hence, the value of Lm is larger than 824.6μH, so as to make sure that Lm operates in CCM. Furthermore, considering the limitation of winding area, the value of Lm is chosen to be 900μH, which is about 1.1 times of the calculated value. Also, the core, named CC4220/JPP44A, is selected to construct Lm along with the corresponding N1 turns of 48 and the required air-gap of 0.628mm. In addition, since n is set at one, the corresponding N2 turns are also 48.

4.3 Design of C1

From Fig. 6(a), the voltage ripple on C1, called ΔvC1 , is composed of the voltage ripple ΔvC1_ESR created from the current flowing through the equivalent series resistor ESRC1, and the voltage ripple ΔvC1_cap created from the charging and discharging of C1 Therefore, ΔvC1 can be expressed to be

Also, ΔvC1_ESR can be represented by

where

where tan δC1 is the dissipation factor of C1.

In addition, ΔvC1_cap can be signified by

where iC1_(1−D) is the current flowing through C1 during the turn-off period.

By assuming the value of ΔvC1 is set at 1% of the rated dc output voltage Vo, substituting (8), (38), (39) and (40) into (37) yields the following rearranged equation:

Based on (25) and (41), the minimum value of C1 occurs under the conditions of the rated dc output power and the minimum dc input voltage. In addition, under the given switching period Ts, the value of 1 tanδC1 is about 13.13 based on the datasheet of Rubycon ZLH series capacitors. Hence, the minimum value of C1 can be calculated to be 1563μF as follows:

Finally, one 2200μF Rubycon capacitor is chosen for C1.

4.4 Design of C2

From Fig. 6(b), the voltage ripple on C2, called ΔvC2 , is composed of the voltage ripple ΔvC2_ESR created from the current flowing through the equivalent series resistor ESRC2, and the voltage ripple ΔvC2_cap created from the charging and discharging of C2. Therefore, ΔvC2 can be expressed to be

Fig. 6.Waveforms pertaining to: (a) C1; (b) C2; (c) Co.

Also, ΔvC2_ESR can be represented by

where

where tan δC2 is the dissipation factor of C2.

Moreover, ΔvC2_cap can be signified by

where iC2 _(1−D) is the current flowing through C2 during the turn-off period.

By assuming that the value of ΔvC2 is set at 0.5% of the rated dc output voltage Vo, substituting (8), (44), (45) and (46) into (43) yields the following rearranged equation:

Based on (25) and (47), the minimum value of C2 occurs under the conditions of the rated dc output power and the minimum dc input voltage. In addition, under the given switching period Ts, the value of tanδC2 is about 6.22 based on the datasheet of Nichicon CS series capacitors. Hence, the minimum value of C2 can be worked out to be 92.3μF as follows:

Eventually, one 220μF Nichicon capacitor is selected for C2.

4.5 Design of Co

From Fig. 6(c), the voltage ripple on Co, called Δvo , is composed of the voltage ripple ΔvCo_ESR created from the current flowing through the equivalent series resistor ESRCo, and the voltage ripple ΔvCo_cap created from the charging and discharging of Co. Therefore, Δvo can be expressed to be

Also, ΔvC2_ESR can be represented by

where

where tanδCo is the dissipation factor of Co.

Besides, ΔvCo_cap can be signified by

where iCo_(D) is the current flowing through Co during the turn-on period.

By assuming that the value of Δvo is set at 0.1% of the rated output voltage Vo, substituting (8), (50), (51) and (52) into (49) yields the following rearranged equation:

Based on (25) and (53), the minimum value of Co occurs under the conditions of the rated dc power and the minimum dc input voltage. In addition, under the given switching period Ts, the value of tanδCo is about 14.14 based on the datasheet of Rubycon CXW series capacitors. Hence, the minimum value of Co can be figured out to be 180.9μF as follows:

At last, two 150μF Rubycon capacitors, one 0.33μF plastic capacitor and one 22nF plastic capacitor are chosen for Co and paralleled together.

4.6 Switch utilization

Like the traditional boost converter, the higher the voltage conversion ratio is, the lower the switch utilization SU [2], which is defined to be

where

Therefore, based on (55), the switch utilization of the proposed converter is about 0.032. This value is quite low due to the corresponding voltage conversion ratio is ultra high, about 20.

 

5. Experimental Results

On the one hand, Fig. 7 shows the waveforms relevant to the input voltage of 24V at rated load. Fig. 7 depicts the gate driving signal for S1, vgs1, and the current in L1, iL1; Fig. 8 shows the gate driving signal for S1, vgs1, the current i3 with the sum of the current in N1, i1, and the current in Lm, iLm, and the current in N2, i2; Fig. 9 depicts the gate driving signal for S1, vgs1, the current in D4, iD4, and the current in S1, iDS1; Fig. 10 shows the gate driving signal for S1, vgs1, and the voltages on C1 and C2, vC1 and vC2; Fig. 11 depicts the gate driving signal for S1, vgs1, and the output voltage ripple Δvo ; Fig. 12 shows the gate driving signal for S1, vgs1, and the voltage on S1, vDS1. From these figures, it can be seen that the proposed converter can operate well to some extent and the output voltage ripple is about 360mV, i.e., 0.09% of Vo, smaller than 0.1% of Vo. Furthermore, it can be seen that from Fig. 12, the voltage across S1 has no voltage spike.

Fig. 7.Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) iL1.

Fig. 8.Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) i3; (3) i2.

Fig. 9.Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) iD4; (3) iDS1.

Fig. 10.Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) vC1; (3) vC2.

Fig. 11.Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) Δvo .

Fig. 12.Measured waveforms under the input voltage of 24V at rated load: (1) vgs1; (2) vDS1.

The following is used to further explain the current spikes on i2 and i3 shown in Fig. 8. Since the proposed converter operates in CCM, the reverse recovery currents created from the diodes are indispensible. Aside from this, in order to reduce the primary and secondary leakage inductances, the bifilar winding technique is adopted, thereby causing the equivalent parasitic capacitance in the transformer to be increased. Furthermore, since the proposed converter is an ultra high step-up converter, the voltage across the transformer is relatively large during the turn-off period, implying that the energy stored in the equivalent parasitic capacitance in the transformer is relatively large. Therefore, based on the mentioned above, high current spikes occur as soon as the switch is turned on. This phenomenon can be seen in the traditional boost converter operating in CCM with a high output voltage. As generally acknowledged, these current spikes will create EMI noises. However, the EMI problem should be taken into account from many aspects, such as EMI choke design, shielding design, layout, etc. Consequently, in this paper, it is very hard to discuss the effects of these current spikes on the EMI problem.

Besides, Figs. 13 and 14 are used to show load transient responses due to step load change from 50% to 100% load and 100% and 50%, respectively. From these figures, it can be seen that the values of two recovery times are both about 1.2V, and the values of the undershoot and overshoot are both within 16ms. And, Fig. 15 shows a photo of the experimental setup.

Fig. 13.Load transient response due to step load change from 50% to 100% load under the rated input voltage.

Fig. 14.Load transient response due to step load change from 100% to 50% load under the rated input voltage.

Fig. 15.Photo of the experimental setup.

Finally, Table 3 makes a comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output. From Table 3, it can be seen that the denominator of the voltage conversion ratio of the proposed converter is the square of one minus duty cycle, and hence, under a given duty cycle and turns ratio, the proposed converter has a higher voltage conversion ratio than all the other references do, but the corresponding voltage stress is higher than all the other voltage stresses. Also, the number of the components is 10, which is acceptable as compared to those used in the References.

Table 3.Comparison between the proposed converter and the converters shown in the References, in terms of voltage conversion ratio, component number, switch voltage stress, output inductor and floating output

 

6. Conclusion

A high step-up converter is presented herein, which combines the traditional buck-boost converter, the charge pump capacitor and the coupling inductor, so as to make the circuit design relatively elastic. Above all, the leakage inductance energy can be recycled to the output, and hence no voltage spike on the switch occurs. In addition, the used power switch is not floating, so as to make the gate driving circuit quite simple. Based on the mentioned above, this converter is very suitable for the green energy applications.