JSTS:Journal of Semiconductor Technology and Science

  • 제15권4호
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  • Pages.506-517
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS

  • Kim, Sang-Yun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Juri (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Park, Hyung-Gu (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Pu, Young Gun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Jae Yong (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2015.05.29
  • 심사 : 2015.08.04
  • 발행 : 2015.08.30
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초록

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

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참고문헌

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