전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제52권6호
  • /
  • Pages.70-76
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  • 2015
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  • 2287-5026(pISSN)
  • /
  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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FPGA 경계 스캔 체인을 재활용한 FPGA 자가 테스트 회로 설계

A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain

  • 윤현식 (한밭대학교 컴퓨터공학과) ;
  • 강태근 (한밭대학교 컴퓨터공학과) ;
  • 이현빈 (한밭대학교 컴퓨터공학과)
  • Yoon, Hyunsik (Department of Computer Engineering, Hanbat National University) ;
  • Kang, Taegeun (Department of Computer Engineering, Hanbat National University) ;
  • Yi, Hyunbean (Department of Computer Engineering, Hanbat National University)
  • 투고 : 2015.03.25
  • 심사 : 2015.05.31
  • 발행 : 2015.06.25
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초록

본 논문은 FPGA 내부의 경계 스캔 체인을 자가 테스트 회로로써 재활용하기 위한 FPGA 자가 테스트 회로 설계 기술을 소개한다. FPGA의 경계 스캔 체인은 테스트나 디버깅 기능뿐만 아니라 각 셀에 연결되어 있는 입출력 핀의 기능을 설정하기 위해서도 사용되기 때문에 일반적인 칩의 경계 스캔 셀보다 매우 크다. 따라서, 본 논문에서는 FPGA 경계 스캔 셀의 구조를 분석하고 소수의 FPGA 로직과 함께 테스트 패턴 생성과 결과 분석이 가능하도록 설계한 BIST(built-in-self-test) 회로를 제시한다. FPGA의 경계 스캔 체인을 자가 테스트를 위하여 재사용함으로써 면적 오버헤드를 줄일 수 있고 보드상에서 프로세서를 사용한 온-라인(on-line) 테스트/모니터링도 가능하다. 실험을 통하여 오버헤드 증가량과 시뮬레이션 결과를 제시한다.

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

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