정보처리학회논문지:컴퓨터 및 통신 시스템 (KIPS Transactions on Computer and Communication Systems)

  • 제4권6호
  • /
  • Pages.177-184
  • /
  • 2015
  • /
  • 2287-5891(pISSN)
  • /
  • 2734-049X(eISSN)
한국정보처리학회 (Korea Information Processing Society)
권호 표지
DOI QR코드

DOI QR Code

주파수 공유형 멀티코어 프로세서를 위한 부하균등화에 기반한 실시간 병렬 작업들의 최소 전력 스케줄링

Minimum-Power Scheduling of Real-Time Parallel Tasks based on Load Balancing for Frequency-Sharing Multicore Processors

  • 이완연 (동덕여자대학교 컴퓨터학과)
  • 투고 : 2014.12.19
  • 심사 : 2015.03.16
  • 발행 : 2015.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 DVFS 기반의 멀티코어 프로세서상에서 실시간 병렬 작업들의 마감시한을 만족하면서 전력 소모량을 최소화시키는 스케줄링 기법을 제안하였다. 제안된 기법에서는 먼저 모든 프로세싱 코어들의 계산부하가 동일해지도록 각 작업에게 할당될 프로세싱 코어들의 실수 개수를 찾는다. 그리고 프로세싱 코어들의 계산부하가 동일하도록 유지하면서 찾은 실수 개수의 프로세싱 코어들을 자연수 개수의 프로세싱 코어들로 변환시켜 각 작업들의 실행에 할당한다. 제안된 방법은 단일 시점에 동일한 속도로 동작하는 주파수 공유형 멀티코어 프로세서의 전력 소모량을 최소화하도록 설계되었다. 성능 평가 실험에서 제안된 기법이 기존 방법의 전력 소모량을 최대 38%까지 감소시킴을 확인하였다.

This paper proposes a minimum-power scheduling scheme of real-time parallel tasks while meeting deadlines of the real-time tasks on DVFS-enabled multicore processors. The proposed scheme first finds a floating number of processing cores to each task so that the computation load of all processing cores would be equalized. Next the scheme translates the found floating number of cores into a natural number of cores while maintaining the computation load of all cores unchanged, and allocates the translated natural number of cores to the execution of each task. The scheme is designed to minimize the power consumption of the frequency-sharing multicore processor operating with the same processing speed at an instant time. Evaluation shows that the scheme saves up to 38% power consumption of the previous method.

키워드

참고문헌

  1. L. Benini, A. Bogliolo, and G. Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Trans. VLSI Syst., Vol.8, No.3, pp.299-316, 2000. https://doi.org/10.1109/92.845896
  2. J. R. Lorch, A. J. Smith, "PACE: a new approach to dynamic voltage scaling," IEEE Trans. Computers, Vol.53, No.7, pp. 856-869, 2004. https://doi.org/10.1109/TC.2004.35
  3. R. Xu, C. Xi, R. Melhem, and D. Moss, "Practical PACE for embedded systems," ACM Int'l Conf. Embedded Software, pp.54-63, 2005.
  4. C. Yang, J. Chen, and T. Kuo, "An approximation algorithm for energy-efficient scheduling on a chip multiprocessor," in Design, Automation and Test in Europe Conf., pp.468-473, 2005.
  5. A. Andrei, P. Eles, Z. Peng, M. T. Schmitz, and B. Hashimi, "Energy optimization of multiprocessor systems on chip by voltage selection," IEEE Trans. VLSI Syst., Vol.15, No.3, pp. 262-275, 2007. https://doi.org/10.1109/TVLSI.2007.891101
  6. C. Xian, Y. Lu, and Z. Li, "Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time," in Design Automation Conf., pp.664-669, 2007.
  7. H. Aydin, Q. Yang, "Energy-aware partitioning for multiprocessor real-time systems," in Int'l Parallel Distributed Processing Symp., pp.113.2, 2003.
  8. E. Seo, J. Jeong, S. Park, and J. Lee, "Energy efficient scheduling of real-time tasks on multicore processors," IEEE Trans. Parallel Distributed Syst., Vol.19, No.1, pp.1540-1552, 2008. https://doi.org/10.1109/TPDS.2008.104
  9. W. Lee, H. Kim, and H. Lee, "Minimum-energy semi-static scheduling of a real-time video stream on DVFS-enabled multi-core processors," IEICE Trans. Information and Systems, Vol.E94-D, No.12, pp.2389-2392, 2011. https://doi.org/10.1587/transinf.E94.D.2389
  10. L. Wang, S. U. Khan, D. Chen, J. Kolodziej, R. Ranjan, C. Xu, and A. Zomaya, "Energy-aware parallel task scheduling in a cluster," Future Generation Computer Systems, Vol.29, pp.1661-1670, 2013. https://doi.org/10.1016/j.future.2013.02.010
  11. W. Lee, "Energy-efficient scheduling of periodic real-time tasks on lightly loaded multi-core processors," IEEE Trans. Parallel Distributed Syst., Vol.23, No.3, pp.530-537, 2012. https://doi.org/10.1109/TPDS.2011.87
  12. K. Lee, "Energy-efficient fault-tolerant scheduling based on duplicated executions for real-time tasks on multicore processors," Journal of the Korea Society of Computer and Information, Vol.19, No.5, pp.1-10, 2014. https://doi.org/10.9708/jksci.2014.19.5.001
  13. D.L. Eager, J. Zahorjan, and E. D. Lozowska, "Speedup versus efficiency in parallel systems," IEEE Trans. Computers, Vol.38, No.3, pp.408-423, 1989. https://doi.org/10.1109/12.21127
  14. E. Talpes, D. Marculescu, "Toward a Multiple Clock/Voltage Island Design Style for Power-Aware Processors," IEEE Trans. Very Large Scale Integration Systems, Vol.13, No.5, pp.591-603, 2005. https://doi.org/10.1109/TVLSI.2005.844305
  15. E. K. Burke, M. Dror, and J. B. Orlin, "Scheduling malleable tasks with interdependent processing rates: comments and observations," Discrete Applied Mathematics, Vol.156, pp. 620-626, 2008. https://doi.org/10.1016/j.dam.2007.08.008
  16. Z. Lan, V. E. Taylor, and G. Bryan, "A novel dynamic load balancing scheme for parallel systems," Journal of Parallel and Distributed Computing, Vol.62, pp.1763-1781, 2002. https://doi.org/10.1016/S0743-7315(02)00008-4
  17. S. Chakravorty, C. L. Mendes, and L. V. Kale, "Proactive fault tolerance in MPI applications via task migration," in Int'l Conf. High Performance Computing, pp.485-496, 2006.