• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.80-84
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• 2009

Dynamic voltage and frequency scaling (DVFS) is an effective method to achieve low power design. In our work, we present an analytical DVFS method which judiciously exploits correlation information in runtime distribution while satisfying deadline constraints. The proposed method overcomes the previous distribution-aware DVFS method [2] which has pessimistic assumption on which runtime distributions are independent. Experimental results show the correlation-aware DVFS offers 13.3% energy reduction compared to existing distribution-aware DVFS [2].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1082-1091
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• 2011

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of KIISE
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• v.43 no.3
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• pp.296-303
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• 2016

Mobile real-time systems with limited system resources and a limited power source need to fully utilize the system resources when the workload is heavy and reduce energy consumption when the workload is light. EDZL (Earliest Deadline until Zero Laxity), a multiprocessor real-time scheduling algorithm, can provide high system utilization, but little work has been done aimed at reducing its energy consumption. This paper tackles the problem of DVFS (Dynamic Voltage/Frequency Scaling) in EDZL scheduling. It proposes a technique to compute a uniform speed on full-chip DVFS platforms and individual speeds of tasks on per-core DVFS platforms. This technique, which is based on the EDZL schedulability test, is a simple but effective one for determining the speeds of tasks offline. We also show through simulation that the proposed technique is useful in reducing energy consumption.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.1-10
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• 2010

As processor platforms are continuously moving toward wireless mobile systems, embedded mobile processors are expected to perform more and more powerful, and therefore the development of an efficient power management algorithm for these battery-operated mobile and handheld systems has become a critical challenge. It is well known that a memory system is a main performance limiter in the processor point of view. Although many DVFS studies have been considered for the efficient utilization of limited battery resources, recent works do not explicitly show the interaction between the processor and the memory. In this research, to properly reflect short/long-term memory access patterns of the embedded workloads in wireless mobile processors, we propose a memory buffer utilization as a new index of DVFS level prediction. The simulation results show that our solution provides 5.86% energy saving compared to the existing DVFS policy in case of memory intensive applications, and it provides 3.60% energy saving on average.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.974-977
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• 2007

본 논문은 성능 카운터를 이용하여 Intel XScale 마이크로아키텍쳐 기반의 Marvell PXA320 프로세서에 대한 성능 모니터링을 구현하였다. Windows CE 운영체제 환경의 응용프로그램에 대하여 DVFS 구성에 따른 각각의 벤치마크를 측정하였고, 성능 이벤트에 따른 성능 카운터 값을 측정 하였다. 성능 모니터링으로 측정된 데이터를 기반으로 DVFS 기법을 위한 스케줄링이 가능하다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.46-53
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• 2013

Recently, intensive research has been performed for reducing video decoder energy consumption, especially based on DVFS (Dynamic Voltage and Frequency Scaling) technique. Our previous work [1] has proposed the optimal DVFS algorithm for energy reduction in video decoders. In spite of the mathematical optimality of the algorithm, the precondition of known frame decoding cycle/complexity limits its application to some realistic scenarios. This paper overcomes this limitation by frame data size-based estimation of frame decoding complexity. The proposed decoding complexity estimation method shows over 90% accuracy. And with this estimation method and buffer underflow margin of around 20% of frame size, almost same power consumption reduction performance as the optimal algorithm can be achieved.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.483-491
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• 2014

Contemporary computer systems exploits DVFS (Dynamic Voltage/Frequency Scaling) technology for balancing performance and power consumption. The efficiency of DVFS depends on how much performance we get for larger power consumption due to elevated CPU frequency. Especially for memory-bounded applications, higher CPU frequency often does not result in higher performance. In this paper, we present an upper bound of CPU frequency scaling based on memory accesses. It is observed that the performance gain due to higher CPU frequency is limited by memory accesses (last level cache misses) per instructions by experiments. Using the results, we present the CPU frequency upper bound with little performance gain. Experimental results show that for a memory-bounded application, applying the frequency upper bound enhances the energy efficiency of the application by above 30%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.854-857
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• 2015

As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.