전기전자학회논문지 (Journal of IKEEE)

  • 제19권1호
  • /
  • Pages.45-51
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  • 2015
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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IEEE 802.15.4 호환 WPAN 기기를 위한 낮은 복잡도를 갖는128-bit AES-CCM* IP 설계

Design of Low-Complexity 128-Bit AES-CCM* IP for IEEE 802.15.4-Compatible WPAN Devices

  • Choi, Injun (Dept. of Electronics Engineering, Chungnam National University) ;
  • Lee, Jong-Yeol (Div. of Electronic Engineering, Chonbuk National University) ;
  • Kim, Ji-Hoon (Dept. of Electronics Engineering, Chungnam National University)
  • 투고 : 2015.01.06
  • 심사 : 2015.03.02
  • 발행 : 2015.03.31
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초록

최근 IoT(Internet of Things) 기기를 위한 근거리 무선 네트워크 시스템이 널리 활용되면서 점차 보안의 필요성이 증가하고 있다. 본 논문에서는 IEEE 802.15.4 호환 WPAN 기기를 위한 낮은 복잡도를 갖는 128-bit AES-$CCM^*$ 하드웨어를 효율적으로 구현하였다. WPAN 기기에서는 하드웨어 자원과 전력 소모가 매우 제한되기 때문에, 다양한 최적화 기법을 적용하여 낮은 복잡도를 갖는 AES-$CCM^*$ 하드웨어를 구현해야 한다. 본 논문은 하드웨어의 복잡도를 줄이기 위해 composite field 연산을 채택하면서 8-bit 데이터 패스를 갖는 folded AES processing core를 제안한다. 또한 IEEE 802.15.4 표준에서 정의된 $CCM^*$ 모드를 지원하기 위해 적은 하드웨어 자원을 사용하며 응답시간이 빠른 토글 구조의 AES-$CCM^*$ 제안한다. 본 논문에서 제안된 AES-$CCM^*$ 하드웨어는 기존의 하드웨어의 57%에 해당하는 게이트 수로 구현가능하다.

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

키워드

참고문헌

  1. FIPS-197:Advanced Encryption Standard, National Institute of Standards and Technology (NIST), 2001
  2. Satoh A., Morioka S., Takano K., Munetoh S., "A Compact Rijndael Hardware Architecture with S-Box Optimization", Theory and Application of Cryptology and Information Security (ASIACRYPT 2001), Gold Coast, Australia, 2001.
  3. C. Paar, "Efficient VLSI architecture for bit-parallel computations in Galois field," Ph.D. dissertation, Institute for Experimental Mathematics, University of Essen, Essen, Germany, 1994.
  4. X. Zhang and K. K. Parhi, "High-speed VLSI architectures for the AES algorithm," IEEE Trans. VLSI Systems, vol. 12, no. 9, pp. 957-967, 2004. https://doi.org/10.1109/TVLSI.2004.832943
  5. Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks(LRWPAN), IEEE Std. 802.15.4, 2006.
  6. Ohyoung Song and Jiho Kim, "An Efficient Design of Security Accelerator for IEEE 802.15.4 Wireless Senor Networks",Consumer Communications and Networking Conference (CCNC), Las Vegas, Jan, 2010.
  7. Lian Huai, Xuecheng Zou, Zhenglin Liu, and Yu Han, "An Energy-Efficient AES-CCM Implementation for IEEE802.15.4 Wireless Sensor Networks", Networks Security, Wireless Communications and Trusted Computing, Wuhan, Hubei, 2009.
  8. Dang Khoa Nguyen, Leonardo Lanante and Hiroshi Ochi, "High Throughput-Resource Saving Hardware Implementation of AES-CCM for Robust Security Network", Journal of Automation and Control Engineering Vol. 1, No. 3, September 2013
  9. IP Cores Inc, CCMZ1/CCMZ2 IEEE 802.15.4 CCM AES Cores, www.ipcores.com/images/ccmzcore.pdf, July 2006

피인용 문헌

  1. Implementation of 868/915 MHz LR-WPAN Transceiver for IoT Systems vol.20, pp.1, 2016, https://doi.org/10.7471/ikeee.2016.20.1.107