An Improved Topology for the Current Fed Parallel Resonant Half Bridge Circuits Used in Fluorescent Lamp Electronic Ballasts

Abstract

An improvement in the current fed parallel resonant half bridge (CFPRHB) circuits used in fluorescent lamp electronic ballasts is provided in this paper. The CFPRHB belongs to the self-oscillating family which includes the current fed push-pull and series resonant inverters, most of which are used in instant-start applications. However, many failure modes are related to the bypass capacitor according to an analysis of failed samples. In this paper, the operating functions of the existing topology in the steady state are analyzed and the main root cause of failure modes has been found. Comparisons between the two topologies are conducted in terms of the voltage stress of the bypass capacitor as well as the thermal and performance of the ballasts to verify the advantages of the proposed topology. It is found that the improved topology is capable of enhancing the reliability and reducing the cost of products without having a negative influence on the system performance.

I. INTRODUCTION

Fluorescent lamps of many types have been studied in [1]-[4], and various kinds of electronic ballasts have been designed as lamp drivers in [5]-[12]. Many topologies have been developed to improve the performance of fluorescent lamps in lighting systems. They can generally be separated into self-oscillating series and IC-controlled series. The self-oscillating ballasts as described in [13]-[17] have been widely used in the market since they have fewer components and lower cost. The self-oscillating families include the current fed push-pull, series and parallel resonant inverters, etc. [18]. The current fed push-pull and series resonant topologies have been well studied. Conversely, the current fed parallel resonant topologies need to be explored further.

The traditional topology for current fed parallel resonant half bridge (CFPRHB) circuits, as shown in Fig. 1, is dealt with in this paper. This topology is often used in ballasts to drive T8 lamps, such as F32T8, F25T8 and F17T8 lamps. It is widely used by international companies in fluorescent lamp electronic ballasts because of its independent lamp operation (ILO), simple structure, perfect isolation between the input and output, fewer components and lower cost.

Fig. 1.Traditional topology of CFPRHB circuit.

It is recorded that many of the failure modes of failed samples returned from applications are related to the bypass capacitor C8 in Fig. 1. Too high of a voltage stress was found on the capacitor at the steady and transient states, which can reduce the lifetime of the capacitor and result in failures of the ballasts.

This paper is organized as follows. Issues and the main root cause of traditional CFPRHBs are described in Section II. An improved topology is proposed and analyzed in Section III. Simulations are presented in Section IV. Experiments and discussions are provided in Section V. Conclusions are given in Section VI.

 

II. ISSUES OF THE TRADITIONAL CFPRHB

A. Operating Principles of the Traditional CFPRHB

The operating principles of the traditional CFPRHB are described as follows. Only the half bridge circuit is depicted in Fig. 1. Before that, there is a power factor correction (PFC) circuit within a single ballast. Since the PFC circuit is not depicted in Fig. 1, the symbols used in the CFPRHB may seem discontinuous. These symbols are defined as follows. Udc is the output voltage of the PFC circuit, which is called the DCBUS. C2 and C3 are in series and each voltage is 0.5Udc. Q1 and Q2 are the transistors used as switches. D1 and D2 are the avalanche and freewheeling diodes. The input AC voltage is from 120V to 277V. When power is on, PFC starts to work and Udc is built up first. Then the startup capacitor C1 is charged by 0.5Udc through T4-1 and R1. Once C1 is charged to the threshold, D3 is on and C1 is discharged through D3 and the base to the emitter junction of Q2. Then, Q2 is on. T2 is the current fed transformer and the primary winding of T4 acts as a resonant inductor, where the self inductance is much smaller than T2. T4-3 and T4-4 are designed as drive windings. T4-2 is the output winding to withstand the Open Circuit Voltage (OCV). There are many branches in parallel with T4-2, each of which consists of a lamp in series with a ballasting capacitor. Co and Rlamp denote the total equivalent ballasting capacitor and the total equivalent resistor of all of the lamps, respectively. C8 is the bypass capacitor and it works with C7 and Co. The parameters used in this paper are listed in Table I. When Q2 is on and Q1 is off, current flows through C3, the tank, Q2, T2-2 and then back to C3. Q2 will saturate as the drive signal is enhanced according to the induced voltage in T4-3. Since the voltage on T4-1 is sinusoidal, the drive signals are also sinusoidal and Q2 will be turned off when the voltage on T4-3 drops below the threshold. Meanwhile, Q1 is on. The freewheeling current flows through C3, the tank, D1, C8, T2-2 and back to C3. When it reverses, the current loop includes C2, T2-1, Q1 and the tank. The same analogy applies to the function when Q1 is on. Then, the circuit enters the self-oscillating mode.

TABLE IPARAMETERS OF THE CIRCUIT

B. Issues Occurred in the Traditional CFPRHB

V-I mapping tests of key components have been implemented and voltage spikes as high as 1.2kV on two switches have been observed before ignition at the worst case, as shown in Fig. 2. Voltages on Q1 and Q2 have been recorded in channels 1 and 2. As analyzed after, these high voltage spikes are also on C8. Their RMS and maximum voltages of are 511V and 722V, respectively, which means that the existing type of MKP21 (700V) can not last long in the applications since it is out of spec.

Fig. 2.Voltage spikes on switches (200V/div, 10μs/div).

To solve this issue, capacitors of higher voltage ratings must be used, which may result in higher cost.

C. Root Cause Analysis of the Failure Modes in the Traditional CFPRHB

To find out the root cause, an analysis of the topology is needed. The operating functions can be separated into two stages. In this paper, stage 1 means Q2 is on and Q1 is off, and stage 2 means Q1 is on and Q2 is off, as shown in Fig. 3. All of the variables are defined in the related figures.

Fig. 3.Equivalent circuits of the traditional CFPRHB at different stages.

According to Kirhhoff’s Voltage Law (KVL), the equations can be obtained from Fig. 3(a) as:

where uo denotes the voltage on T4-1, ut represents the voltage on each of the windings of T2, uC8 denotes the voltage on C8, and uQ1 denotes the voltage on Q1.

Substituting Eqns. (1)-(2) into Eq. (3) gives:

According to KVL, the equations of Fig. 3 (b) are:

Substituting Eqns. (5)-(6) into Eq. (7) gives:

In Fig. 1, uo is the AC voltage, the mean value of which is zero. The power direction is from A to B at stage 1, while it is opposite at stage 2. Thus, Eq. (4) and Eq. (8) can be rewritten into a uniform equation, which is expressed as:

It is observed from Eq. (9) that the transient voltage on C8 is always twice that of uo , which explains the reason why he peak voltage on C8 is over 1kV at the worst case. Such high voltage spikes may damage the bypass capacitor.

 

III. PROPOSED TOPOLOGY OF THE CFPRHB

A. Improved Topology and Its Operation Principle

The key concept is to find a way to change the form of Eq. (9), so that it can reduce the absolute value of uC8.

An improved topology is proposed, as shown in Fig. 4. When compared with the traditional topology, the positions of T2 and C8 are changed, while all of the other parameters in the main circuit are kept the same.

Fig. 4.The improved topology of CFPRHB.

B. Comparison of the Operating Functions between the Two Topologies

Similarly, the analysis of the operating functions can also be separated into two stages, as shown in Fig. 5. The equations can be obtained from Fig. 5 (a) as:

Fig. 5.Operating stages of the improved CFPRHB.

By substituting Eq. (10) into Eq. (12) and Eq. (11), the following is obtained:

In Fig. 5 (b), the equations can be expressed as:

Substituting Eq. (15) into Eq. (16) and Eq. (17) gives:

Eq. (13) and Eq. (18) can be rewritten into a united form to get the voltage formula of the switches, which can be expressed as:

Similarly, the following can be obtained:

A great change in the voltage on C8 can be observed by comparing Eq. (9) and Eq. (21). In the traditional topology, the peak voltage value of C8 is always twice that of uo while it is changed to be less than Udc in the improved topology.

C. An Example of the Solution

With the example and parameters in Table I, it is possible to obtain Uo = UC7RMS = 225 V.

Let then in the proposed topology, the voltage of C8 can be expressed as:

which means:

Eq. (23) indicates that transient voltage on C8 will not exceed max which means that the peak value is less than Udc. When compared to the 722V in the traditional CFPRHB, the improved CFPRHB has an overwhelming advantage on reducing voltage stress of C8.

The RMS voltage of C8 in the improved topology can be calculated through Eq. (22), which is:

Based on Eq. (24) and the parameters in Table I, the calculated RMS voltage of C8 is 221.6V, which is much less than the 511V in the traditional CFPRHB.

D. Modeling of the Improved Topology

The main concept is to build up equivalent circuits of each stage using Thevenin’s theorem.

The impedance between B and C in Fig. 6 is expressed as:

Fig. 6.Equivalent circuit of Fig. 5 (a).

According to Eq. (25), the simplified operating function can be depicted as Fig. 7.

Fig. 7.Simplified operating stages of the improved CFPRHB.

The two operating functions can be further united as shown in Fig. 8.

Fig. 8.Equivalent circuits of the improved CFPRHB.

In Fig. 8, Lr denotes the inductance of the primary winding of T4, Lm denotes the inductance of each winding of T2, Rla and Cla are the equivalent resistor and capacitor looking from the primary side to the secondary side of T4, which are:

With respect to the equivalent circuits in Fig. 8 (b), the relationship between the self-oscillating frequency and the circuit parameters can be expressed as:

Where, m denotes the numbers of ballasting capacitors. In this paper, m is equal to 4.

 

IV. SIMULATION

To verify the aforementioned analysis, simulations are carried out by LTSpice. The parameters of the main circuit are the same in the two topologies, as described in Table I. All of the lamps are regarded as pure resistors in the simulation.

A. Verification of the Voltages of C8

The simulated voltage waveforms are shown in Fig. 9, where (a) and (b) are the results of the traditional and improved topologies, respectively. It can be seen that the shapes of the two waveforms are different. The waveform in Fig. 9 (b) is the inverse type of Fig. 9 (a). Both the peak and RMS voltages of the improved topology are much less than the traditional one. This is in agreement with the theoretical analysis.

Fig. 9.Simulated voltage waveforms of C8 at steady state.

B. Verification of the Lamp Current

The lamp current in each topology at the steady state is compared in Fig. 10 to double check whether it is influenced or not after the topology improvement. Obviously, the simulation results show that the lamp current is not affected based on the same parameters of the main circuit.

Fig. 10.Simulated waveforms of lamp current at steady state.

 

V. EXPERIMENTS AND DISCUSSIONS

A. Voltage Comparison

To double check the effectiveness of the proposed topology, an experimental study has been conducted. The switches are 1.1kV/4A transistors and the diodes are 1kV/1A avalanche types. Their parameters are the same as those in Table I.

The experimental waveforms of the voltage of C8 at the steady state are shown in Fig. 11. In the traditional topology, the peak value is 730V and the RMS value is 514V, while they are 450V and 237V in the improved topology. The test results are consistent with both the simulation results and the theoretical analysis.

Fig. 11.Measured voltage waveforms of C8 at steady state.

The start-up state is also checked as shown in Fig. 12. The solution behaves well at the worst case when the input voltage is 305VAC and at the start-up state. The voltage spike of C8 is 450V which is clamped by the DC voltage according to Eq. (23). This is also consistent with the theoretical analysis.

Fig. 12.Measured voltage waveform of C8 at start-up state@305 VAC input (500V/div, 0.5s/div).

B. Thermal Comparison

As mentioned, there are two parts in the tested sample, one is the boost PFC and the other one is the half bridge circuit, as shown in Fig. 13.

Fig. 13.Experimental setup for thermal tests.

Thermal tests have been implemented on the same ballast. Some traces in the printed circuit board (PCB) are modified to change the traditional topology into the improved one. However, the positions of all of the components have not been changed in the PCB. Two thermal tests are conducted for the self-rise test of C8. The thermal couple is located at the same capacitor and the capacitor is also located at the same position in the ballast. The only difference is that the capacitor works normally in the first test but does not work in the second test, while an additional capacitor is working at another place instead. The thermal gap of the capacitor between the two tests is defined as the self-rise of C8.

The thermal tests are conducted at room temperature and the results are shown in Table II. All of the data are close except for the self-rise of C8 which decreases from 5.5 ℃ to 2.5 ℃ based on the same input power. It is known that the thermal tests of C8 are related to its RMS voltage. The reason why they decrease is that voltage stress is reduced in the improved CFPRHB. This validates the effectiveness of the topology improvement.

TABLE IITHERMAL DATA OF TWO TOPOLOGIES

C. Performance Comparison

Tests are also conducted to double check the performance under 277V of input, as shown in Table III. The crest factor is defined as the ratio of the maximum value to the RMS value of the lamp current, which is the key objective in the design and should be less than 1.7. There is no obvious difference in the tested performance data between the two topologies with the same parameters, which are shown in Table I.

TABLE IIIPERFORMANCE DATA OF TWO TOPOLOGIES

Considering parts A, B and C in this section, it is validated by the experimental results that the topology improvement can solve the issue of the voltage stress on C8 and with less influence on the system performance.

D. Other V-I mapping Tests

To validate the performance of the designed prototype, more current and voltage waveforms with descriptions are presented in Fig. 14 to Fig. 18.

Fig. 14.Measured waveforms of the PFC MOSFET. Ch1: Current waveform, 1A/div, Ch2: Voltage waveform, 200V/div.

The waveforms of the MOSFE in the boost PFC circuit are shown in Fig. 14 where the current and voltage waveforms are shown in Ch1 and Ch2, respectively. The tested results of the MOSFET at the steady state when the input voltage is 120V are recorded in Fig. 14(a). It can be seen that the frequency of the envelopes of both of the waveforms is 100Hz which is twice that of the AC source. The input voltage of the PFC circuit is 100Hz since it is obtained through a single-phase rectifier from the AC source. The PFC circuit is designed at the critical continuous mode which can be further validated by Fig. 14(b), the zooming of Fig. 14(a) and the fact that the input voltage is 108V. When the MOSFET is off, its voltage rises to a high level and the current decreases to zero. When it starts to be turned on, the current increases linearly and starts from zero which indicates that the current through the boost inductor increases from zero during each switching period.

The DC output of the PFC circuit is called the DCBUS, as shown in Fig. 15. It can be seen from Fig. 15(a) that the RMS value of the DCBUS is 460.8V at the steady state. The transient response is shown in Fig. 15(b). The peak value is 490V which is within the specs of the electrolytic capacitor used in the prototype.

Fig. 15.Measured waveforms of DCBUS of PFC circuit.

The voltage and current waveforms of a single ballasting capacitor are presented in Fig. 16. The ballasting capacitors are in series with lamps which means they have the same current. It can be seen from Ch1 that the RMS value of the tested voltage is 551V, which supports more voltage pressure than the lamp after ignition. This is the same as the design.

Fig. 16.Measured waveforms of each ballasting capacitor at steady state. Ch1: Voltage waveform, 1000V/div, Ch2: Current waveform, 0.5A/div.

The voltage and current waveforms of the switch Q2 are shown in Fig. 17. The voltage and current waveforms from the collector to the emitter at both the steady and transient states are shown in Fig. 17(a) and 17(b), respectively. It can be seen that the peak values at the transient state are much larger than that those at the steady state. However, both are within the specs. The voltage and current waveform from the base to the emitter are shown in Fig. 17(c). As described in Section II, the driving winding T4-3 is designed for Q1 and T4-4 is for Q2, each of which is only 1 turn and the driving signal is sinusoidal. When the driving voltage rises to the threshold of the base to the emitter junction, Q2 will be on and the base current Ib is kept sinusoidal, as seen in Ch1 of Fig. 17(c). It can also be observed that when Vbe decreases to the threshold, there is a huge reversing recovery current of Ib. However, a peak value of -465mA can meet the specifications. All of the waveforms of the other switch Q1 are similar.

Fig. 17.Measured waveforms of Q2. Ch1: Voltage waveform, Ch2: Current waveform.

The voltage and current waveforms of T4-1 are shown in Fig. 18. The tested RMS voltage value is 255.4V, which is the same as that analyzed in Part C of Section III. It can be seen that the current rises when the voltage is positive and reverses when the voltage is negative. The tested peak value of the current is about 1.59A under which T4 doesnot saturate and can work well.

Fig. 18.Measured waveforms of T4-1. Ch1: Voltage waveform, 500V/div, Ch2: Current waveform, 2A/div.

 

VI. CONCLUSION

This paper analyzes the high voltage stress on the bypass capacitor in a traditional CFPRHB. This reveals the root cause of the failure modes of ballasts with this topology. An improved topology of a CFPRHB is then proposed. The operating principles and modeling of the proposed topology are also provided. Both a theoretical analysis and simulations have been carried out. They show that the voltage stress on C8 in the proposed CFPRHB is significantly reduced without having a negative influence on the system performance. Hence, a capacitor with lower voltage ratings for C8 can be used and the cost will be reduced accordingly. The proposed topology offers the advantages of higher reliability and lower cost when compared with the traditional one. Several experiments have also been carried out. They verify both the theoretical analysis and the effectiveness of the proposed CFPRHB.