Steady-State Analysis of ZVS and NON-ZVS Full-Bridge Inverters with Asymmetrical Control for Induction Heating Applications

Abstract

This paper presents a steady-state operation analysis of full-bridge series-resonant inverters focusing on the distorted load current due to low-quality-factor resonant circuits in induction heating and other applications. The regions of operation based on the zero-voltage switching (ZVS) and non-zero-voltage switching (NON-ZVS) operations of the asymmetrical voltage-cancellation control technique are identified. The effects of a distorted load current under a wide range of output powers are also analyzed for achieving a precise ZVS operating region. An experimental study is performed with a 1kW prototype. Simulation and experimental studies have confirmed the validity of the proposed method. An efficiency comparison between the variable frequency method and the conventional fixed-frequency method is provided.

I. INTRODUCTION

High-frequency resonant inverters for induction heating (IH) technologies have been widely used in industrial, automotive, pipeline and consumer applications where high efficiency, system reliability, safety, cleanliness, compactness in volumetric physical size, light weight, and performance are required [1]. The use of a higher switching frequency results in higher switching losses, resulting in a lowered efficiency. However, this switching loss can greatly be reduced by the soft-switching technique [2]-[6]. The zero-voltage switching (ZVS) technique is one of the soft-switching techniques. It is the representative feature of resonant inverters and is suitable for high-switching frequency operation. The ZVS operation avoids switching losses, reduces electromagnetic interference (EMI) and device stresses, and allows for the possibility of snubberless operation [4], [7]-[10]. Voltage-source resonant inverter topologies have received a great deal of attention because of their output power control capability under ZVS operation. Several switching techniques have been reported in high-frequency IH applications such as the pulse-frequency modulation (PFM) [11]-[13], pulse-density modulation (PDM) [14], [15], asymmetrical duty-cycle (ADC) [16], [17], phase-shift (PS) [18]-[20], and asymmetrical voltage-cancellation (AVC) [21]-[24]. In [24], the variable-frequency AVC control is used in a full-bridge resonant inverter with a low-quality-factor resonant circuit (Qr) to identify the condition of ZVS operation by the fundamental harmonic approximation technique. However, this technique may not guarantee ZVS operation in the entire range of output power. By using the AVC technique in the case of a low Qr resonant circuit (less than 2.5 [25]), the output current (load current) is non-sinusoidal due to a high damping factor (α) value. The transient response is oscillatory and exponentially damped in nature. The output current is unavoidably distorted and may result in hard-switching conditions during switching transitions at the end of the positive cycle, causing the so-called nonzero-voltage switching (NON-ZVS). Consequently, an increase in the switching losses and device stresses results in a lower efficiency.

In practice, the switching loss due to the effect of the parasitic capacitances associated with the charging and discharging of switching devices has been observed during a switching transition period. To mitigate this switching loss, the positive output current diverted from the resonant circuit should be large enough to completely discharge the parasitic capacitors and the switching frequency must be suitably increased above the resonant frequency.

The regions of ZVS and NON-ZVS operations of the full-bridge inverters for IH applications with a low Qr resonant circuit based on the asymmetrical control technique have been identified in this paper. The influence of parasitic capacitors are taken into consideration through computer simulations and verified by experimental results. The remainder of this paper consists of six sections. The circuit configurations and operations are described in Section II. Section III presents a steady state circuit analysis. In Section IV, an analysis of the soft-switching operation is provided. The experimental setup and results are provided in Section V. Section VI concludes the work.

 

II. CIRCUIT CONFIGURATION AND OPERATIONS

A. Circuit Configuration

Fig. 1 shows a full-bridge series-resonant inverter circuit for induction heating applications. A voltage-source inverter consisting of four IGBTs (S1 -S4) with antiparallel diodes (D1 -D4) and parasitic capacitors (C1 -C4 or Co), is connected with a series-resonant load. To eliminate the turn-on switching loss, all of the switches (S1 -S4) are operated at a frequency slightly higher than the resonant frequency under the ZVS condition.

Fig. 1.Circuit configuration of full-bridge series-resonant inverter.

B. Steady-State ZVS Operation

The gate signals for the switching devices (S1 -S4) and typical steady-state waveforms of the output voltage and current of the inverter for ZVS and NON-ZVS operations are shown in Fig. 2. As shown in Fig. 2(a), the inverter operates with the desired ZVS operation. Figs. 2(b) and (c) show steadystate waveforms for the NON-ZVS operations. The output power Po is adjusted by varying the shifted angle β through switch S4. The output voltage vo of the inverter assumes the form of a square wave while the output current io is lagging the output voltage by the angle θio at the end of the positive cycle of io. θCo is an angle defined at the completion of charging and discharging processes of C1 and C2, respectively. The fundamental components of the output voltage and current are illustrated by the sinusoidal signals Vo1 and Io1, respectively. The Io1 signal lags the Vo1 signal by the phase angle θz1. The modes of operation with ZVS are described in eight stages (t0 -t4), as illustrated in Fig. 3 by the solid arrows.

Fig. 2.The gate signals for all switches and typical steady-state waveforms of the output voltage and current. (a) Desired ZVS. (b) NON-ZVS I. (c) NON-ZVS II.

Mode 1 (t0−t'0): The switches S2 and S3 are already turned off, and the switches S1 and S4 are still off. Negative output current flows through the parasitic capacitors C1, C2, C3 and C4. The parasitic capacitors C2and C3 are completely charged by the Leq-Cr resonant circuit while the parasitic capacitors C1 and C4 are completely discharged. At the same time, the output voltage increases from -VDC to +VDC. From the Laplace transform, the output current io and voltage vo during this mode are given as follows:

where: is the initial value of the output current io, and A1=-2V0-VC1+VC2+VC3-VC4 is the total initial voltage of the capacitor in each mode when V0 is the initial voltage of the resonant capacitor Cr. VC1, VC2, VC3, and VC4 are the initial voltages of the parasitic capacitors C1, C2, C3, and C4, respectively.

Mode 2 (t'0−t1): At t'0, the switches S2 and S3 are still off. The negative output current is diverted from the parasitic capacitors C1 and C4 to the antiparallel diodes D1 and D4. Then it reaches zero at t1. After the switch dead time td, the switches S1 and S4 receive positive gating signals and the output voltage is equal to +VDC. The current io and voltage vo in this mode are expressed as:

where:

Mode 3 (t1−t'1): At t1, the switches S1 and S4 start conducting after the antiparallel diodes D1 and D4 are turned off, and the ZVS operation is obtained. The positive output current flows from zero until t'1, and the output voltage is still equal to +VDC. At this stage, the current io and voltage vo in this mode are expressed as:

where:

Mode 4 (t'1−t2): At t'1, while the switch S1 still conducts, the switch S4 is turned off due to the shifted angle β that is adjusted to control the output power. During this mode, the output current flows in the same direction. The parasitic capacitor C4 is charged while the parasitic capacitor C3 is discharged. At this stage, the output voltage decreases to zero. The current io and voltage vo are expressed as:

where:

Mode 5 (t2−t'2): At t2, with a given value of the shifted angle β, the switch S4 is already turned off while the switch S1 still conducts and the output current flows through the antiparallel diode D3. During this stage, the output voltage is already zero and the positive output current is decreasing. The current io and voltage vo become:

where:

Mode 6 (t'2−t3): At t'2, all of the switches are off. A part of the positive output current flows through the antiparallel diode D3 and the parasitic capacitors C1 and C2. At the same time, the capacitor voltage VC1 increases from zero to +VDC, whereas the capacitor voltage VC2 decreases from +VDC to zero. In this mode, the output voltage reduces from zero to -VDC at t3. The current io and voltage vo are:

where:

Mode 7 (t3−t'3): At t3, the switch S1 is still off during the dead time. The antiparallel diodes D2 and D3 naturally conduct while the positive output current decreases to zero at t'3. At this stage, the output voltage is equal to -VDC. The switches S2 and S3 receive the same positive gating signal. Therefore, the current io and voltage vo in this mode are:

where:

Mode 8 (t'3−t4): At t'3, as soon as the antiparallel diodes D2 and D3 are turned off, the switches S2 and S3 conduct under ZVS operation. During this stage, the output current and voltage are both negative and a full cycle of waveform is achieved. This can be expressed by:

where:

C. NON-ZVS Operation

Two NON-ZVS operations have been observed as illustrated in Fig. 3. The first one emanated from an increase in the shifted angle β with the aim of reducing the output power without varying the switching frequency fs. The first category of NON-ZVS operations (NON-ZVS I) is indicated by the dashed arrows where the previously described operation of mode 7 is replaced by mode 7'. Mode 6 begins after the gate signal of S1 is removed at t'2, as depicted in Fig. 2(b). The positive output current flows through the circuit formed by C1, C2, D3, and the DC input voltage source. During this interval, the capacitor voltage VC1 increases whereas the capacitor voltage VC2 decreases. The output voltage becomes negative in this mode. At the beginning of mode 7', after the antiparallel diode D3 is turned off at t3 with no gate signals of S2 and S3, the output current becomes negative and flows through the parasitic capacitors C1, C2, C3 and C4. Therefore, the voltages across the switches S2 and S3 increase. At t'3, the switches S2 and S3 start conducting under the NON-ZVS. The parasitic capacitors C1 and C2experience an instantaneous voltage change. This results in high current spikes in the switches S1 and S2. In this case, the modes of operation are sequenced as

Fig. 3.Operation modes of a full-bridge resonant inverter: (a) desired ZVS, (b) NON-ZVS I, and (c) •••► NON-ZVS II.

The second category of NON-ZVS operations (NON-ZVS II) is indicated by the dotted arrows in Fig. 3. It can also be divided into eight stages as The original operations of modes 6 and 7 in the ZVS operation are changed to modes 6' and 7", respectively. The operation in mode 6' begins when the positive output current becomes zero at t'2 before the end of the gate signal of S1, depicted in Fig. 2(c). The negative output current flows through the antiparallel diode D1 and the parasitic capacitors C3 and C4. During this mode, the capacitor voltage VC3 increases whereas the capacitor voltage VC4 decreases, adding up to a high value for the output voltage depending on the operating frequency. At the same time, the capacitor voltages VC1 and VC2 remain unchanged at zero and +VDC, respectively. Mode 7" begins at t3. The switches S2 and S3 start conducting instantaneously under the NON-ZVS operation. Since the capacitor voltage VC1 is initially zero, this creates a short-circuit path of the input voltage source through the switch S2. All of the parasitic capacitors suffer from a sudden voltage change that results in current spikes in the capacitors (C1-C4) and the switches S2 and S3 for a short interval. Such an operation reduces the inverter efficiency due to the high turn-on switching loss and it causes device stress, which may destroy all of the switches.

Therefore, for the case of a low Qr resonant circuit, the damping frequency ωd of the series-resonant circuit is less than the resonant angular frequency ωr due to a high damping factor α. Two NON-ZVS operations on the switches S2 and S3 are likely to be encountered if the inverter is operated at an unsuitable switching frequency.

 

III. STEADY STATE CIRCUIT ANALYSIS

The induction heating load can be modeled as an equivalent resistor (Req) and inductor (Leq). The resonant circuit is formed by adding a resonant capacitor (Cr), as shown in Fig. 1. The load quality factor of the resonant circuit is defined as:

where fr is the resonant frequency, and

A steady-state analysis of the series-resonant circuit is based on the equivalent parameters and typical waveforms under the ZVS operation as shown in Fig. 1 and Fig. 2(a), respectively. To simplify the analysis, the conventional assumptions are made for the analysis in this section as follows.

With the stated assumption, the magnitude of the impedance Ẑeq of the series-resonant circuit can be obtained as:

where h is the order of harmonic components, and fn is the normalized frequency (fs/fr).

The impedance phase angle of the harmonic components is given by:

The output voltage is given by:

The amplitude of the harmonic components of the output voltage can be written by means of the Fourier series as:

where β is the shifted angle of the switch S4 with a value from 0º to 180º, and VDC is the DC bus voltage. The angle θvh between the output voltage vo and its harmonic voltage (Voh) can be determined by:

The output current can also be written by:

where the angle θih is the phase difference between the output voltage and the impedance phase angle (θih=θvh-θzh). The amplitude of the harmonic components of the output current is given by:

Note that if the load quality factor is sufficiently high (more than 2.5), the output current io flowing through the series-resonant circuit assumes the form of a sinusoidal wave. In addition, the angle θio in Fig. 2(a) can be reasonably approximated by the phase difference θi1.

From (16), the average output power Po is given as:

The maximum value of the output power in (17) occurs at fn = 1 and β = 0. Clearly, if the normalized frequency fn and β are increased, the output power is reduced, as shown in Fig. 4 (i.e., an increase of β will result in a reduction of the output power). However, the minimum output power is limited to 25% of the maximum output power at β =180º since the output voltage control is through an adjustment of the positive cycle and the minimum achievable output voltage is at 50% of its rated value [21].

Fig. 4.The relationship of percent output power, β, and fn.

 

IV. ANALYSIS OF THE SOFT-SWITCHING OPERATION

A necessary requirement for the ZVS operation of a fullbridge resonant inverter with the asymmetrical voltage-cancellation control technique is that the applied voltage across the switches must be zero during the turn-on operation. Although, the switching frequency of the series-resonant inverter is higher than the resonant frequency, the NON-ZVS operations may occur due to an increase in the shifted angle β, resulting in a variation of the angle θv1, as shown in Fig. 5. From Fig. 2(a), neglecting the parasitic capacitances, the ZVS condition requires that the angle θio must be greater than zero. This means that the positive output current waveforms become zero after the end of the gate signal S1 (i.e., the antiparallel diodes D2 and D3 provide a path for the energy stored in the resonant circuit that must be conducted at t'2).

Fig. 5.The angle θv1 as a function of shifted angle β.

In practice, the inverter is operated at high frequencies and the effects of the parasitic capacitors can be significant. They can alter the predetermined ZVS operation during a switching transition at the end of the positive cycle of io. The discharging processes of the parasitic capacitor C2 must be complete before the output current reaches zero (i.e., the output current should be large enough to ensure the ZVS condition). Therefore, the output current continues to flow through the antiparallel diodes D2 and D3. The critical angle of the parasitic capacitors is calculated by:

where Co is the parasitic capacitor of the switch, and io(t)t=π is the output current at 180º.

The angle θCo,cri may be used to define a proper dead time interval. The critical ZVS boundary of operation is obtained by setting θio = θCo,cri = θtd in (15) where θtd is an angle of the dead time td. The critical ZVS boundary under the effect of Co is obtained as indicated by the solid line while neglecting Co as indicated by the dotted line in Fig. 6. If the load quality factor is high, for example Qr = 5, the boundary line is rather flat with fn around 1.06 at 110º of the shifted angle β. On the other hand, at Qr = 1, the highest boundary value of fn will shift to around 80º of the shifted angle β. Therefore, the regions of ZVS and the two NON-ZVS operations can be identified in terms of fn as described in Section II. Again, the dotted line is the boundary between the NON-ZVS I and the NON-ZVS II operations (where θio = 0) whereas the solid line is the boundary between the desired ZVS and the NON-ZVS I operations. This implies that a switching frequency higher than the solid line will ensure the ZVS operation. If the shifted angle β is adjusted to 60º, fn must be more than 1.24 to guarantee the ZVS operation. In addition, the conventional AVC control with fixed frequency control requires the inverter to operate above the resonant frequency (i.e. fs > fr) and the highest boundary value of fn, specifically fn > 1.26 for this case, at all times.

Fig. 6.Regions of ZVS and NON-ZVS operations in terms of fn.

 

V. EXPERIMENTAL SETUP AND RESULTS

A. Experimental Setup

A hardware prototype is created where an induction cooker is used to illustrate the proposed analysis on the low Qr resonant circuit. The system controller is an STM32F4 discovery board. To avoid acoustic noise from the induction coil and the cooking vessel, the resonant frequency must be over 20 kHz. The material used in the cooking vessel is essential in terms of efficiency. The cooking vessel is an off-the-shelf low-cost vessel made of stainless steel that measures 235 mm in diameter and 75 mm in height. The bottom and wall thicknesses are 1.4 mm and 0.8 mm, respectively.

The induction coil is a 29-turn flat spiral made of a litz wire consisting of 35 strands of 26 SWG wire to reduce the skin effect losses and the consequent increase of heat in the coil. The maximum coil current is approximately 12 A rms. A resonant capacitor Cr of 300 nF, 1000 V has been selected to provide the resonant frequency at 33 kHz, and the quality factor Qr at resonance is approximately one. Note that the resonant capacitor needs to withstand the peak voltage, which may be greater than the DC input voltage because of voltage magnification due to the circuit quality factor.

The inverter specifications and circuit parameters are given in Table I. The dead time interval td is chosen as 320 ns based on the manufacturer’s data sheet. For the complete ZVS condition, the angle θio must be higher than the angle θtd, as shown in Fig. 2(a). As mentioned before, an increase of the shifted angle β will cause a reduction of the angle θio. In this experiment, the angle θio is set at 7º by controlling the switching frequency. In the worst case scenario, where the shifted angle β is around 80º, the switching frequency must increase to 45.5 kHz (fn = 1.37) so that the angle θio becomes 7º (425 ns). Thus, the switching frequency of the inverter is varied between 33.75 kHz and 45.5 kHz to assure operation in the desired ZVS region as shown in Fig. 6.

TABLE IINVERTER SPECIFICATIONS AND CIRCUIT PARAMETERS

B. Simulation and Experimental Results

A computer simulation is performed to illustrate the proposed boundaries of the ZVS and NON-ZVS operations using the inverter specifications and circuit parameters from Table I. To demonstrate the inverter operation in the ZVS, critical ZVS, NON-ZVS I, and NON-ZVS II regions, the corresponding switching frequencies are set to 45.5, 40.5, 39.5 and 36 kHz, respectively. In addition, the shifted angle β is initially set at 80º.

The steady-state phase plane trajectories of the current and voltage of the inverter (io and vo) and the switches (iS2 and vS2) for the desired ZVS, critical ZVS, and two NON-ZVS operations are shown in Fig. 7. In Fig. 7(a), the switch current iS2 is negative while the switch voltage vS2 decreases from +VDC to zero at t3. The negative current iS2 flows through the diode D2 then reaches zero at t'3, and ZVS operation is achieved. Under the critical ZVS operation, it can be seen that the switch voltage vS2, indicated in Fig. 7(b), decreases from +VDC to zero while the small negative value of the switch current iS2 also flows through the capacitor C2. With an increase in the shifted angle β to reduce the output power, the angle θio decreases and becomes less than the angle θtd. The inverter operates in the NON-ZVS I region as indicated in Fig. 7(c). The negative switch current iS2 crosses zero and becomes positive while the switch voltage vS2 is still positive. This causes a current spike in the switch S2 during the turn-on transition. Although this current spike is not likely to damage the switch, the inverter’s efficiency is sacrificed. Fig. 7(d) shows the phase plane trajectory under the operation of the NON-ZVS II. At t'2, the output current io is negative flowing through the diode D1, before the switch S1 is turned off. The output voltage vo is exposed to the increasing voltage across the capacitor C3, causing a current spike several times the normal current on the switches S2 and S3. Clearly, the current spike in the NON-ZVS II operation can cause damage to the switches.

Fig. 7.Phase-plane trajectories of the current and voltage of the inverter and the switch S2. (a) Desired ZVS. (b) Critical ZVS. (c) NON-ZVS I. (d) NON-ZVS II.

The relationship between the angle θio and the shifted angle β at various switching frequencies fs is shown in Fig. 8. The output power regulation through the shifted angle β has an obvious effect on the angle θio. An unsuitable switching frequency can lead to ZVS or NON-ZVS operations. For instance, if the output power is set to the desired value at β = 80º. The switching frequency fs at 45.5 kHz yields an operation in the ZVS region because the angle θio is greater than the angle θCo,cri at 4.7º (where fs = 40.5 kHz). On the other hand, a switching frequency fs at 39.5 kHz causes the angle θio to become less than the angle θCo,cri. This is an operation in the NON-ZVS I region. Note that if the angle θio is further decreased, through a switching frequency reduction, the inverter is operated in the NON-ZVS II region. In other words, the angle θio becomes negative as indicated by the dashed line.

Fig. 8.Relationship between the angle θio and the shifted angle β at various switching frequencies fs.

The simulation and experimental results under the desired ZVS and two NON-ZVS operations are shown in Figs. 9 and 10. The results under the ZVS operation are shown in Figs. 9(a) and 10(a). The switching frequency of the inverter is then adjusted (45.5 kHz), according to Fig. 6, where the angle θio becomes 7º over the angle θCo,cri to assure operation in the desired ZVS region. The results under the operation of the NON-ZVS I are shown in Figs. 9(b) and 10(b) where the angle θio is at 3.2º to allow for operation in the NON-ZVS I region. In addition, the NON-ZVS II results are shown in Figs. 9(c) and 10(c) where the angle θio is -11º. For the NON-ZVS operations, as observed in the results, the switches S1 and S4 are turned on at zero voltage, but the switches S2 and S3 are turned on at non-zero voltage due to the load parameters and unsuitable switching frequency. This results in high switching losses in switches S2 and S3 which in turn reduces the inverter efficiency. In the case of the NON-ZVS II, the current spikes at the turn-on switching period may cause damages to the switches S2 and S3.

Fig. 9.Simulation waveforms of vo, io, vS2, iS2, vS4 and iS4 at β = 80º for: (a) Desired ZVS region with fs = 45.5 kHz. (b) NON-ZVS I region with fs = 39.5 kHz. (c) NON-ZVS II region with fs = 36 kHz. (vo: 50V/div, io: 5A/div,vS2: 50V/div, iS2: 5A/div, vS4: 50V/div, iS4: 5A/div and Time: 5us/div.).

Fig. 10.Experimental waveforms of vo, io, vS2, iS2, vS4 and iS4 at β = 80º for: (a) Desired ZVS region with fs = 45.5 kHz. (b) NON-ZVS I region with fs = 39.5 kHz. (c) NON-ZVS II region with fs = 36 kHz. (vo: 50V/div, io: 5A/div,vS2: 50V/div, iS2: 5A/div, vS4: 50V/div, iS4: 5A/div and Time: 5us/div.).

C. Efficiency

An efficiency comparison between the proposed variable frequency and conventional fixed-frequency methods for AVC schemes are provided as shown in Fig. 11. As mentioned earlier, the switching frequency of the fixed-frequency method is set to 45.5 kHz while the switching frequency of the variable frequency method is in the range of 33.75-45.5 kHz. Clearly, the variable frequency control yields a higher efficiency, especially in the low output power range, since the switching frequency is allowed to decrease. The benefits of knowing the regions of operation are the insight into the optimal operation as a systematic approach while maintaining the ZVS operation throughout all of the output power levels.

Fig. 11.Efficiency comparison between the variable frequency and the conventional fixed-frequency methods.

 

VI. CONCLUSION

This paper addresses the issue of the regions of ZVS and NON-ZVS operations of a full-bridge inverter focusing on the distorted load current due to a low-quality-factor resonant circuit in induction heating and other applications. The steady-state circuit analysis is based on the asymmetrical control scheme and a Fourier series analysis. The operations of ZVS and NON-ZVS are analyzed in terms of the typical waveform phenomenon of the inverter and the analytical equations in the operation modes. Under the ZVS operating criteria, the parasitic capacitances must also be taken into account. The presented circuit configurations and operations provide insight into the selection of optimal operation with the soft-switching technique to achieve a high efficiency. In addition, this method can be applied to other applications.