JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs

  • Lee, Junan (Dept. of Electronic Engineering, Sogang University) ;
  • Huang, Qiwei (Dept. of Electronic Engineering, Sogang University) ;
  • Kim, Kiwoon (Dept. of Electronic Engineering, Sogang University) ;
  • Kim, Kyunghoon (Dept. of Electronic Engineering, Sogang University) ;
  • Burm, Jinwook (Dept. of Electronic Engineering, Sogang University)
  • Received : 2014.08.25
  • Accepted : 2014.12.26
  • Published : 2015.02.28
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Abstract

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

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References

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