전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제52권2호
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  • Pages.195-200
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  • 2015
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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시간-디지털 변환기를 이용한 ADPLL의 잡음 개선에 대한 연구

A Study on the Noise Improvement of All Digital Phase-Locked Loop Using Time-to-Digital Converter

  • 안태원 (동양미래대학교 전기전자통신공학부) ;
  • 이종석 (숭실대학교 전자정보공학부) ;
  • 이원석 (동양미래대학교 전기전자통신공학부) ;
  • 문용 (숭실대학교 전자정보공학부)
  • Ahn, Tae-Won (School of Electrical Engineering, Dongyang Mirae University) ;
  • Lee, Jongsuk (School of Electronic Engineering, Soongsil University) ;
  • Lee, Won-Seok (School of Electrical Engineering, Dongyang Mirae University) ;
  • Moon, Yong (School of Electronic Engineering, Soongsil University)
  • 투고 : 2014.12.16
  • 심사 : 2015.01.26
  • 발행 : 2015.02.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 ADPLL의 잡음 개선을 위해 8비트 SVBS-TDC (Semi-Vernier Binary-Search Time-to-Digital Converter)를 제안했다. TDC의 동작 속도를 높이기 위해 인코더 등 디지털 블록을 사용하지 않는 BS-TDC (Binary-Search TDC) 구조를 사용했으며, 버니어 구조를 적용하여 기존의 BS-TDC에 비해 해상도를 10배 이상 증가시켰다. TDC의 단점인 좁은 입력범위를 개선하기 위해 버니어 구조를 절반만 적용하여 510ps의 넓은 입력 범위를 확보했다. 제안하는 SVBS-TDC는 65nm CMOS 공정으로 설계하였고, 모의실험 결과 1.2V 전원 전압에서 동작 속도는 200MHz이고 해상도는 4ps로서 ADPLL의 잡음 특성을 효과적으로 개선함을 확인하였다.

This paper presents SVBS-TDC (Semi-Vernier Binary-Search Time-to-Digital Converter) for the noise improvement of ADPLL (All-Digital Phase Locked Loop. We used a Semi-Vernier BS-TDC (Binary-Search TDC) architecture to improve the operation speed more then 10 times compared with the previous conventional BS-TDC and ensured a 510ps wide input range. The proposed Semi-Vernier BS-TDC was designed in a 65ns CMOS process and the simulation results showed 200MHz speed and 4ps resolution with a 1.2V supply voltage, and considerable noise improvement of ADPLL.

키워드

참고문헌

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